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15
16#ifndef __CONFIG_H
17#define __CONFIG_H
18
19
20#define CONFIG_MP 1
21#define CONFIG_LINUX_RESET_VEC 0x100
22#define CONFIG_ADDR_MAP 1
23
24
25
26
27
28#define CONFIG_SYS_TEXT_BASE 0xeff00000
29
30#ifdef RUN_DIAG
31#define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE
32#endif
33
34
35
36
37
38#define CONFIG_SYS_SCRATCH_VA 0xe0000000
39
40#define CONFIG_SYS_SRIO
41#define CONFIG_SRIO1
42
43#define CONFIG_PCIE1 1
44#define CONFIG_PCIE2 1
45#define CONFIG_FSL_PCI_INIT 1
46#define CONFIG_SYS_PCI_64BIT 1
47
48#define CONFIG_TSEC_ENET
49#define CONFIG_ENV_OVERWRITE
50
51#define CONFIG_BAT_RW 1
52#define CONFIG_HIGH_BATS 1
53#define CONFIG_SYS_NUM_ADDR_MAP 8
54
55#define CONFIG_ALTIVEC 1
56
57
58
59
60#define CONFIG_SYS_L2
61#define L2_INIT 0
62#define L2_ENABLE (L2CR_L2E)
63
64#ifndef CONFIG_SYS_CLK_FREQ
65#ifndef __ASSEMBLY__
66extern unsigned long get_board_sys_clk(unsigned long dummy);
67#endif
68#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
69#endif
70
71#define CONFIG_SYS_MEMTEST_START 0x00200000
72#define CONFIG_SYS_MEMTEST_END 0x00400000
73
74
75
76
77
78
79#ifdef CONFIG_PHYS_64BIT
80#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f
81#else
82#define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000
83#endif
84
85
86
87
88
89#define CONFIG_SYS_CCSRBAR 0xffe00000
90#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
91
92
93#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
94#define CONFIG_SYS_CCSRBAR_PHYS_HIGH CONFIG_SYS_PHYS_ADDR_HIGH
95#define CONFIG_SYS_CCSRBAR_PHYS \
96 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
97 CONFIG_SYS_CCSRBAR_PHYS_HIGH)
98
99#define CONFIG_HWCONFIG
100
101
102
103
104#undef CONFIG_FSL_DDR_INTERACTIVE
105#define CONFIG_SPD_EEPROM
106#define CONFIG_DDR_SPD
107
108#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
109#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
110
111#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
112#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
113#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000
114#define CONFIG_VERY_BIG_RAM
115
116#define CONFIG_DIMM_SLOTS_PER_CTLR 2
117#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
118
119
120
121
122#define SPD_EEPROM_ADDRESS1 0x51
123#define SPD_EEPROM_ADDRESS2 0x52
124#define SPD_EEPROM_ADDRESS3 0x53
125#define SPD_EEPROM_ADDRESS4 0x54
126
127
128
129
130#define CONFIG_SYS_SDRAM_SIZE 256
131#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
132#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
133#define CONFIG_SYS_DDR_TIMING_3 0x00000000
134#define CONFIG_SYS_DDR_TIMING_0 0x00260802
135#define CONFIG_SYS_DDR_TIMING_1 0x39357322
136#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
137#define CONFIG_SYS_DDR_MODE_1 0x00480432
138#define CONFIG_SYS_DDR_MODE_2 0x00000000
139#define CONFIG_SYS_DDR_INTERVAL 0x06090100
140#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
141#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
142#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
143#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
144#define CONFIG_SYS_DDR_CONTROL 0xe3008000
145#define CONFIG_SYS_DDR_CONTROL2 0x04400000
146
147#define CONFIG_ID_EEPROM
148#define CONFIG_SYS_I2C_EEPROM_NXID
149#define CONFIG_ID_EEPROM
150#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
151#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
152
153#define CONFIG_SYS_FLASH_BASE 0xef800000
154#define CONFIG_SYS_FLASH_BASE_PHYS_LOW CONFIG_SYS_FLASH_BASE
155#define CONFIG_SYS_FLASH_BASE_PHYS \
156 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
157 CONFIG_SYS_PHYS_ADDR_HIGH)
158
159#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
160
161#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
162 | 0x00001001)
163#define CONFIG_SYS_OR0_PRELIM 0xff806ff7
164
165#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \
166 | 0x00001001)
167#define CONFIG_SYS_OR2_PRELIM 0xffffeff7
168
169#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \
170 | 0x00000801)
171#define CONFIG_SYS_OR3_PRELIM 0xffffeff7
172
173
174
175
176
177
178#define CONFIG_SYS_LBC_BASE 0xffde0000
179#define CONFIG_SYS_LBC_BASE_PHYS_LOW CONFIG_SYS_LBC_BASE
180
181#define CONFIG_FSL_PIXIS 1
182#define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000)
183#define PIXIS_BASE_PHYS_LOW (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000)
184#define PIXIS_BASE_PHYS PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \
185 CONFIG_SYS_PHYS_ADDR_HIGH)
186#define PIXIS_SIZE 0x00008000
187#define PIXIS_ID 0x0
188#define PIXIS_VER 0x1
189#define PIXIS_PVER 0x2
190#define PIXIS_RST 0x4
191#define PIXIS_AUX 0x6
192#define PIXIS_SPD 0x7
193#define PIXIS_VCTL 0x10
194#define PIXIS_VCFGEN0 0x12
195#define PIXIS_VCFGEN1 0x13
196#define PIXIS_VBOOT 0x16
197#define PIXIS_VBOOT_FMAP 0x80
198#define PIXIS_VBOOT_FBANK 0x40
199#define PIXIS_VSPEED0 0x17
200#define PIXIS_VSPEED1 0x18
201#define PIXIS_VCLKH 0x19
202#define PIXIS_VCLKL 0x1A
203#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40
204
205
206#define CF_BASE (PIXIS_BASE + PIXIS_SIZE)
207#define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE)
208
209#define CONFIG_SYS_MAX_FLASH_BANKS 1
210#define CONFIG_SYS_MAX_FLASH_SECT 128
211
212#undef CONFIG_SYS_FLASH_CHECKSUM
213#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
214#define CONFIG_SYS_FLASH_WRITE_TOUT 500
215#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
216#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000
217
218#define CONFIG_FLASH_CFI_DRIVER
219#define CONFIG_SYS_FLASH_CFI
220#define CONFIG_SYS_FLASH_EMPTY_INFO
221
222#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
223#define CONFIG_SYS_RAMBOOT
224#else
225#undef CONFIG_SYS_RAMBOOT
226#endif
227
228#if defined(CONFIG_SYS_RAMBOOT)
229#undef CONFIG_SPD_EEPROM
230#define CONFIG_SYS_SDRAM_SIZE 256
231#endif
232
233#undef CONFIG_CLOCKS_IN_MHZ
234
235#define CONFIG_SYS_INIT_RAM_LOCK 1
236#ifndef CONFIG_SYS_INIT_RAM_LOCK
237#define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000
238#else
239#define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000
240#endif
241#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
242
243#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
244#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
245
246#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
247#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
248
249
250#define CONFIG_CONS_INDEX 1
251#define CONFIG_SYS_NS16550_SERIAL
252#define CONFIG_SYS_NS16550_REG_SIZE 1
253#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
254
255#define CONFIG_SYS_BAUDRATE_TABLE \
256 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
257
258#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
259#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
260
261
262
263
264#define CONFIG_SYS_I2C
265#define CONFIG_SYS_I2C_FSL
266#define CONFIG_SYS_FSL_I2C_SPEED 400000
267#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
268#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
269#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
270
271
272
273
274#define CONFIG_SYS_SRIO1_MEM_BASE 0x80000000
275#ifdef CONFIG_PHYS_64BIT
276#define CONFIG_SYS_SRIO1_MEM_PHYS_LOW 0x00000000
277#define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x0000000c
278#else
279#define CONFIG_SYS_SRIO1_MEM_PHYS_LOW CONFIG_SYS_SRIO1_MEM_BASE
280#define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x00000000
281#endif
282#define CONFIG_SYS_SRIO1_MEM_PHYS \
283 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
284 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH)
285#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000
286
287
288
289
290
291
292#define CONFIG_SYS_PCIE1_NAME "ULI"
293#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
294#ifdef CONFIG_PHYS_64BIT
295#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
296#define CONFIG_SYS_PCIE1_MEM_PHYS_LOW 0x00000000
297#define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x0000000c
298#else
299#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT
300#define CONFIG_SYS_PCIE1_MEM_PHYS_LOW CONFIG_SYS_PCIE1_MEM_VIRT
301#define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x00000000
302#endif
303#define CONFIG_SYS_PCIE1_MEM_PHYS \
304 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
305 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH)
306#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
307#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
308#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
309#define CONFIG_SYS_PCIE1_IO_PHYS_LOW CONFIG_SYS_PCIE1_IO_VIRT
310#define CONFIG_SYS_PCIE1_IO_PHYS \
311 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
312 CONFIG_SYS_PHYS_ADDR_HIGH)
313#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
314
315#ifdef CONFIG_PHYS_64BIT
316
317
318
319
320
321#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS
322#else
323#define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \
324 + CONFIG_SYS_PCIE1_MEM_SIZE)
325#endif
326#define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \
327 + CONFIG_SYS_PCIE1_MEM_SIZE)
328#define CONFIG_SYS_PCIE2_MEM_PHYS_LOW (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \
329 + CONFIG_SYS_PCIE1_MEM_SIZE)
330#define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH CONFIG_SYS_PCIE1_MEM_PHYS_HIGH
331#define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \
332 + CONFIG_SYS_PCIE1_MEM_SIZE)
333#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000
334#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
335#define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \
336 + CONFIG_SYS_PCIE1_IO_SIZE)
337#define CONFIG_SYS_PCIE2_IO_PHYS_LOW (CONFIG_SYS_PCIE1_IO_PHYS_LOW \
338 + CONFIG_SYS_PCIE1_IO_SIZE)
339#define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \
340 + CONFIG_SYS_PCIE1_IO_SIZE)
341#define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE
342
343#if defined(CONFIG_PCI)
344
345#define CONFIG_PCI_SCAN_SHOW
346
347#undef CONFIG_EEPRO100
348#undef CONFIG_TULIP
349
350
351
352
353#define CONFIG_PCI_OHCI 1
354#define CONFIG_USB_OHCI_NEW 1
355#define CONFIG_SYS_USB_EVENT_POLL 1
356#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
357#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
358#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
359
360
361#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
362
363
364
365
366
367
368#if defined(CONFIG_VIDEO)
369#define CONFIG_BIOSEMU
370#define CONFIG_ATI_RADEON_FB
371#define CONFIG_VIDEO_LOGO
372#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT
373#endif
374
375#undef CONFIG_PCI_SCAN_SHOW
376
377#define CONFIG_SCSI_AHCI
378
379#ifdef CONFIG_SCSI_AHCI
380#define CONFIG_LIBATA
381#define CONFIG_SATA_ULI5288
382#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
383#define CONFIG_SYS_SCSI_MAX_LUN 1
384#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
385#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
386#endif
387
388#endif
389
390#if defined(CONFIG_TSEC_ENET)
391
392#define CONFIG_MII 1
393
394#define CONFIG_TSEC1 1
395#define CONFIG_TSEC1_NAME "eTSEC1"
396#define CONFIG_TSEC2 1
397#define CONFIG_TSEC2_NAME "eTSEC2"
398#define CONFIG_TSEC3 1
399#define CONFIG_TSEC3_NAME "eTSEC3"
400#define CONFIG_TSEC4 1
401#define CONFIG_TSEC4_NAME "eTSEC4"
402
403#define TSEC1_PHY_ADDR 0
404#define TSEC2_PHY_ADDR 1
405#define TSEC3_PHY_ADDR 2
406#define TSEC4_PHY_ADDR 3
407#define TSEC1_PHYIDX 0
408#define TSEC2_PHYIDX 0
409#define TSEC3_PHYIDX 0
410#define TSEC4_PHYIDX 0
411#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
412#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
413#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
414#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
415
416#define CONFIG_ETHPRIME "eTSEC1"
417
418#endif
419
420#ifdef CONFIG_PHYS_64BIT
421#define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
422#define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
423
424
425#define BAT_PHYS_ADDR(low, high) \
426 (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high))
427
428#define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32))
429#else
430
431#define BAT_PHYS_ADDR(low, high) (low)
432#define PAIRED_PHYS_TO_PHYS(low, high) (low)
433#endif
434
435
436
437
438#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
439#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
440
441
442
443
444#define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
445 CONFIG_SYS_PHYS_ADDR_HIGH) \
446 | BATL_PP_RW | BATL_CACHEINHIBIT | \
447 BATL_GUARDEDSTORAGE)
448#define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \
449 | BATU_VS | BATU_VP)
450#define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
451 CONFIG_SYS_PHYS_ADDR_HIGH) \
452 | BATL_PP_RW | BATL_MEMCOHERENCE)
453#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
454
455
456
457
458
459
460#ifdef CONFIG_PCI
461#define CONFIG_PCI_INDIRECT_BRIDGE
462#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
463 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
464 | BATL_PP_RW | BATL_CACHEINHIBIT \
465 | BATL_GUARDEDSTORAGE)
466#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \
467 | BATU_VS | BATU_VP)
468#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
469 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
470 | BATL_PP_RW | BATL_CACHEINHIBIT)
471#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
472#else
473#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
474 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
475 | BATL_PP_RW | BATL_CACHEINHIBIT | \
476 BATL_GUARDEDSTORAGE)
477#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \
478 | BATU_VS | BATU_VP)
479#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
480 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
481 | BATL_PP_RW | BATL_CACHEINHIBIT)
482#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
483#endif
484
485
486
487
488#define CONFIG_SYS_DBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
489 CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
490 | BATL_PP_RW | BATL_CACHEINHIBIT \
491 | BATL_GUARDEDSTORAGE)
492#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
493 | BATU_VP)
494#define CONFIG_SYS_IBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
495 CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
496 | BATL_PP_RW | BATL_CACHEINHIBIT)
497#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
498
499#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
500#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
501 | BATL_PP_RW | BATL_CACHEINHIBIT \
502 | BATL_GUARDEDSTORAGE)
503#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
504 | BATU_BL_1M | BATU_VS | BATU_VP)
505#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
506 | BATL_PP_RW | BATL_CACHEINHIBIT)
507#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
508#endif
509
510
511
512
513#define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
514 CONFIG_SYS_PHYS_ADDR_HIGH) \
515 | BATL_PP_RW | BATL_CACHEINHIBIT \
516 | BATL_GUARDEDSTORAGE)
517#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \
518 | BATU_VS | BATU_VP)
519#define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
520 CONFIG_SYS_PHYS_ADDR_HIGH) \
521 | BATL_PP_RW | BATL_CACHEINHIBIT)
522#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
523
524
525
526
527#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
528#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
529#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
530#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
531
532
533
534
535#define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
536 CONFIG_SYS_PHYS_ADDR_HIGH) \
537 | BATL_PP_RW | BATL_CACHEINHIBIT \
538 | BATL_GUARDEDSTORAGE)
539#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
540 | BATU_VP)
541#define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
542 CONFIG_SYS_PHYS_ADDR_HIGH) \
543 | BATL_PP_RW | BATL_MEMCOHERENCE)
544#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
545
546
547#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
548 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
549#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
550#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
551 | BATL_MEMCOHERENCE)
552#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
553
554
555
556
557#define CONFIG_SYS_DBAT7L 0x00000000
558#define CONFIG_SYS_DBAT7U 0x00000000
559#define CONFIG_SYS_IBAT7L 0x00000000
560#define CONFIG_SYS_IBAT7U 0x00000000
561
562
563
564
565#ifndef CONFIG_SYS_RAMBOOT
566 #define CONFIG_ENV_IS_IN_FLASH 1
567 #define CONFIG_ENV_ADDR \
568 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
569 #define CONFIG_ENV_SECT_SIZE 0x10000
570#else
571 #define CONFIG_ENV_IS_NOWHERE 1
572 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
573#endif
574#define CONFIG_ENV_SIZE 0x2000
575
576#define CONFIG_LOADS_ECHO 1
577#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
578
579
580
581
582#define CONFIG_BOOTP_BOOTFILESIZE
583#define CONFIG_BOOTP_BOOTPATH
584#define CONFIG_BOOTP_GATEWAY
585#define CONFIG_BOOTP_HOSTNAME
586
587
588
589
590#define CONFIG_CMD_REGINFO
591
592#if defined(CONFIG_PCI)
593 #define CONFIG_CMD_PCI
594 #define CONFIG_SCSI
595#endif
596
597#undef CONFIG_WATCHDOG
598
599
600
601
602#define CONFIG_SYS_LONGHELP
603#define CONFIG_CMDLINE_EDITING
604#define CONFIG_SYS_LOAD_ADDR 0x2000000
605
606#if defined(CONFIG_CMD_KGDB)
607 #define CONFIG_SYS_CBSIZE 1024
608#else
609 #define CONFIG_SYS_CBSIZE 256
610#endif
611
612#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
613#define CONFIG_SYS_MAXARGS 16
614#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
615
616
617
618
619
620
621#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
622#define CONFIG_SYS_BOOTM_LEN (256 << 20)
623
624#if defined(CONFIG_CMD_KGDB)
625 #define CONFIG_KGDB_BAUDRATE 230400
626#endif
627
628
629
630
631
632#define CONFIG_HAS_ETH0 1
633#define CONFIG_HAS_ETH1 1
634#define CONFIG_HAS_ETH2 1
635#define CONFIG_HAS_ETH3 1
636
637#define CONFIG_IPADDR 192.168.1.100
638
639#define CONFIG_HOSTNAME unknown
640#define CONFIG_ROOTPATH "/opt/nfsroot"
641#define CONFIG_BOOTFILE "uImage"
642#define CONFIG_UBOOTPATH u-boot.bin
643
644#define CONFIG_SERVERIP 192.168.1.1
645#define CONFIG_GATEWAYIP 192.168.1.1
646#define CONFIG_NETMASK 255.255.255.0
647
648
649#define CONFIG_LOADADDR 0x10000000
650
651#undef CONFIG_BOOTARGS
652
653#define CONFIG_BAUDRATE 115200
654
655#define CONFIG_EXTRA_ENV_SETTINGS \
656 "netdev=eth0\0" \
657 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
658 "tftpflash=tftpboot $loadaddr $uboot; " \
659 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
660 " +$filesize; " \
661 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
662 " +$filesize; " \
663 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
664 " $filesize; " \
665 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
666 " +$filesize; " \
667 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
668 " $filesize\0" \
669 "consoledev=ttyS0\0" \
670 "ramdiskaddr=0x18000000\0" \
671 "ramdiskfile=your.ramdisk.u-boot\0" \
672 "fdtaddr=0x17c00000\0" \
673 "fdtfile=mpc8641_hpcn.dtb\0" \
674 "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \
675 "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
676 "maxcpus=2"
677
678#define CONFIG_NFSBOOTCOMMAND \
679 "setenv bootargs root=/dev/nfs rw " \
680 "nfsroot=$serverip:$rootpath " \
681 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
682 "console=$consoledev,$baudrate $othbootargs;" \
683 "tftp $loadaddr $bootfile;" \
684 "tftp $fdtaddr $fdtfile;" \
685 "bootm $loadaddr - $fdtaddr"
686
687#define CONFIG_RAMBOOTCOMMAND \
688 "setenv bootargs root=/dev/ram rw " \
689 "console=$consoledev,$baudrate $othbootargs;" \
690 "tftp $ramdiskaddr $ramdiskfile;" \
691 "tftp $loadaddr $bootfile;" \
692 "tftp $fdtaddr $fdtfile;" \
693 "bootm $loadaddr $ramdiskaddr $fdtaddr"
694
695#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
696
697#endif
698