1/* 2 * Configuation settings for the Renesas Solutions Migo-R board 3 * 4 * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9#ifndef __MIGO_R_H 10#define __MIGO_R_H 11 12#define CONFIG_CPU_SH7722 1 13#define CONFIG_MIGO_R 1 14 15#define CONFIG_CMD_SDRAM 16 17#define CONFIG_BAUDRATE 115200 18#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01" 19 20#define CONFIG_DISPLAY_BOARDINFO 21#undef CONFIG_SHOW_BOOT_PROGRESS 22 23/* SMC9111 */ 24#define CONFIG_SMC91111 25#define CONFIG_SMC91111_BASE (0xB0000000) 26 27/* MEMORY */ 28#define MIGO_R_SDRAM_BASE (0x8C000000) 29#define MIGO_R_FLASH_BASE_1 (0xA0000000) 30#define MIGO_R_FLASH_BANK_SIZE (64 * 1024 * 1024) 31 32#define CONFIG_SYS_TEXT_BASE 0x8FFC0000 33#define CONFIG_SYS_LONGHELP /* undef to save memory */ 34#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ 35#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ 36#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ 37#define CONFIG_SYS_BARGSIZE 512 /* Buffer size for Boot Arguments passed to kernel */ 38#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */ 39 40/* SCIF */ 41#define CONFIG_SCIF_CONSOLE 1 42#define CONFIG_CONS_SCIF0 1 43 44#define CONFIG_SYS_MEMTEST_START (MIGO_R_SDRAM_BASE) 45#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) 46 47/* Enable alternate, more extensive, memory test */ 48#undef CONFIG_SYS_ALT_MEMTEST 49/* Scratch address used by the alternate memory test */ 50#undef CONFIG_SYS_MEMTEST_SCRATCH 51 52/* Enable temporary baudrate change while serial download */ 53#undef CONFIG_SYS_LOADS_BAUD_CHANGE 54 55#define CONFIG_SYS_SDRAM_BASE (MIGO_R_SDRAM_BASE) 56/* maybe more, but if so u-boot doesn't know about it... */ 57#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) 58/* default load address for scripts ?!? */ 59#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) 60 61/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ 62#define CONFIG_SYS_MONITOR_BASE (MIGO_R_FLASH_BASE_1) 63/* Monitor size */ 64#define CONFIG_SYS_MONITOR_LEN (128 * 1024) 65/* Size of DRAM reserved for malloc() use */ 66#define CONFIG_SYS_MALLOC_LEN (256 * 1024) 67#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 68 69/* FLASH */ 70#define CONFIG_SYS_FLASH_CFI 71#define CONFIG_FLASH_CFI_DRIVER 72#undef CONFIG_SYS_FLASH_QUIET_TEST 73/* print 'E' for empty sector on flinfo */ 74#define CONFIG_SYS_FLASH_EMPTY_INFO 75/* Physical start address of Flash memory */ 76#define CONFIG_SYS_FLASH_BASE (MIGO_R_FLASH_BASE_1) 77/* Max number of sectors on each Flash chip */ 78#define CONFIG_SYS_MAX_FLASH_SECT 512 79 80/* if you use all NOR Flash , you change dip-switch. Please see MIGO_R01 Manual. */ 81#define CONFIG_SYS_MAX_FLASH_BANKS 1 82#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * MIGO_R_FLASH_BANK_SIZE) } 83 84/* Timeout for Flash erase operations (in ms) */ 85#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 86/* Timeout for Flash write operations (in ms) */ 87#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 88/* Timeout for Flash set sector lock bit operations (in ms) */ 89#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 90/* Timeout for Flash clear lock bit operations (in ms) */ 91#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 92 93/* Use hardware flash sectors protection instead of U-Boot software protection */ 94#undef CONFIG_SYS_FLASH_PROTECTION 95#undef CONFIG_SYS_DIRECT_FLASH_TFTP 96 97/* ENV setting */ 98#define CONFIG_ENV_IS_IN_FLASH 99#define CONFIG_ENV_OVERWRITE 1 100#define CONFIG_ENV_SECT_SIZE (128 * 1024) 101#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 102#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 103/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ 104#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) 105#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 106 107/* Board Clock */ 108#define CONFIG_SYS_CLK_FREQ 33333333 109#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 110#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 111#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */ 112 113#endif /* __MIGO_R_H */ 114