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9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12#include "../board/freescale/common/ics307_clk.h"
13
14#ifdef CONFIG_SDCARD
15#define CONFIG_SPL_MMC_MINIMAL
16#define CONFIG_SPL_FLUSH_IMAGE
17#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
18#define CONFIG_SYS_TEXT_BASE 0x11001000
19#define CONFIG_SPL_TEXT_BASE 0xf8f81000
20#define CONFIG_SPL_PAD_TO 0x20000
21#define CONFIG_SPL_MAX_SIZE (128 * 1024)
22#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
23#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
24#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
25#define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
26#define CONFIG_SYS_MPC85XX_NO_RESETVEC
27#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
28#define CONFIG_SPL_MMC_BOOT
29#ifdef CONFIG_SPL_BUILD
30#define CONFIG_SPL_COMMON_INIT_DDR
31#endif
32#endif
33
34#ifdef CONFIG_SPIFLASH
35#define CONFIG_SPL_SPI_FLASH_MINIMAL
36#define CONFIG_SPL_FLUSH_IMAGE
37#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
38#define CONFIG_SYS_TEXT_BASE 0x11001000
39#define CONFIG_SPL_TEXT_BASE 0xf8f81000
40#define CONFIG_SPL_PAD_TO 0x20000
41#define CONFIG_SPL_MAX_SIZE (128 * 1024)
42#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
43#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
44#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
45#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
46#define CONFIG_SYS_MPC85XX_NO_RESETVEC
47#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
48#define CONFIG_SPL_SPI_BOOT
49#ifdef CONFIG_SPL_BUILD
50#define CONFIG_SPL_COMMON_INIT_DDR
51#endif
52#endif
53
54#define CONFIG_NAND_FSL_ELBC
55#define CONFIG_SYS_NAND_MAX_ECCPOS 56
56#define CONFIG_SYS_NAND_MAX_OOBFREE 5
57
58#ifdef CONFIG_NAND
59#ifdef CONFIG_TPL_BUILD
60#define CONFIG_SPL_NAND_BOOT
61#define CONFIG_SPL_FLUSH_IMAGE
62#define CONFIG_SPL_NAND_INIT
63#define CONFIG_SPL_COMMON_INIT_DDR
64#define CONFIG_SPL_MAX_SIZE (128 << 10)
65#define CONFIG_SPL_TEXT_BASE 0xf8f81000
66#define CONFIG_SYS_MPC85XX_NO_RESETVEC
67#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
68#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
69#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
70#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
71#elif defined(CONFIG_SPL_BUILD)
72#define CONFIG_SPL_INIT_MINIMAL
73#define CONFIG_SPL_FLUSH_IMAGE
74#define CONFIG_SPL_TEXT_BASE 0xff800000
75#define CONFIG_SPL_MAX_SIZE 4096
76#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
77#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
78#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
79#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
80#endif
81#define CONFIG_SPL_PAD_TO 0x20000
82#define CONFIG_TPL_PAD_TO 0x20000
83#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
84#define CONFIG_SYS_TEXT_BASE 0x11001000
85#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
86#endif
87
88
89#define CONFIG_MP
90
91#ifndef CONFIG_SYS_TEXT_BASE
92#define CONFIG_SYS_TEXT_BASE 0xeff40000
93#endif
94
95#ifndef CONFIG_RESET_VECTOR_ADDRESS
96#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
97#endif
98
99#define CONFIG_PCIE1
100#define CONFIG_PCIE2
101#define CONFIG_PCIE3
102#define CONFIG_FSL_PCI_INIT
103#define CONFIG_FSL_PCIE_RESET
104#define CONFIG_SYS_PCI_64BIT
105
106#define CONFIG_ENABLE_36BIT_PHYS
107
108#ifdef CONFIG_PHYS_64BIT
109#define CONFIG_ADDR_MAP
110#define CONFIG_SYS_NUM_ADDR_MAP 16
111#endif
112
113#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
114#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
115#define CONFIG_ICS307_REFCLK_HZ 33333000
116
117
118
119
120#define CONFIG_L2_CACHE
121#define CONFIG_BTB
122
123#define CONFIG_SYS_MEMTEST_START 0x00000000
124#define CONFIG_SYS_MEMTEST_END 0x7fffffff
125
126#define CONFIG_SYS_CCSRBAR 0xffe00000
127#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
128
129
130
131#ifdef CONFIG_SPL_BUILD
132#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
133#endif
134
135
136#define CONFIG_DDR_SPD
137#define CONFIG_VERY_BIG_RAM
138
139#ifdef CONFIG_DDR_ECC
140#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
141#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
142#endif
143
144#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
145#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
146
147#define CONFIG_DIMM_SLOTS_PER_CTLR 1
148#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
149
150
151#define CONFIG_SYS_SPD_BUS_NUM 1
152#define SPD_EEPROM_ADDRESS 0x51
153
154
155#define CONFIG_SYS_SDRAM_SIZE 2048
156#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
157#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
158#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
159#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F
160#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202
161#define CONFIG_SYS_DDR_TIMING_3 0x00010000
162#define CONFIG_SYS_DDR_TIMING_0 0x40110104
163#define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746
164#define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca
165#define CONFIG_SYS_DDR_MODE_1 0x00441221
166#define CONFIG_SYS_DDR_MODE_2 0x00000000
167#define CONFIG_SYS_DDR_INTERVAL 0x0a280100
168#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
169#define CONFIG_SYS_DDR_CLK_CTRL 0x02800000
170#define CONFIG_SYS_DDR_CONTROL 0xc7000008
171#define CONFIG_SYS_DDR_CONTROL_2 0x24401041
172#define CONFIG_SYS_DDR_TIMING_4 0x00220001
173#define CONFIG_SYS_DDR_TIMING_5 0x02401400
174#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
175#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608
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197
198
199#define CONFIG_SYS_FLASH_BASE 0xe8000000
200#ifdef CONFIG_PHYS_64BIT
201#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull
202#else
203#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
204#endif
205
206#define CONFIG_FLASH_BR_PRELIM \
207 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
208#define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7)
209
210#ifdef CONFIG_NAND
211#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM
212#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM
213#else
214#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM
215#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM
216#endif
217
218#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
219#define CONFIG_SYS_FLASH_QUIET_TEST
220#define CONFIG_FLASH_SHOW_PROGRESS 45
221
222#define CONFIG_SYS_MAX_FLASH_BANKS 1
223#define CONFIG_SYS_MAX_FLASH_SECT 1024
224
225#ifndef CONFIG_SYS_MONITOR_BASE
226#ifdef CONFIG_SPL_BUILD
227#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
228#else
229#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
230#endif
231#endif
232
233#define CONFIG_FLASH_CFI_DRIVER
234#define CONFIG_SYS_FLASH_CFI
235#define CONFIG_SYS_FLASH_EMPTY_INFO
236
237
238#if defined(CONFIG_NAND_FSL_ELBC)
239#define CONFIG_SYS_NAND_BASE 0xff800000
240#ifdef CONFIG_PHYS_64BIT
241#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
242#else
243#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
244#endif
245
246#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
247#define CONFIG_SYS_MAX_NAND_DEVICE 1
248#define CONFIG_CMD_NAND 1
249#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
250#define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
251
252
253#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
254 | (2<<BR_DECC_SHIFT) \
255 | BR_PS_8 \
256 | BR_MS_FCM \
257 | BR_V)
258#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
259 | OR_FCM_PGS \
260 | OR_FCM_CSCT \
261 | OR_FCM_CST \
262 | OR_FCM_CHT \
263 | OR_FCM_SCY_1 \
264 | OR_FCM_TRLX \
265 | OR_FCM_EHTR)
266#ifdef CONFIG_NAND
267#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
268#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
269#else
270#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
271#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
272#endif
273
274#endif
275
276#define CONFIG_BOARD_EARLY_INIT_R
277#define CONFIG_MISC_INIT_R
278#define CONFIG_HWCONFIG
279
280#define CONFIG_FSL_NGPIXIS
281#define PIXIS_BASE 0xffdf0000
282#ifdef CONFIG_PHYS_64BIT
283#define PIXIS_BASE_PHYS 0xfffdf0000ull
284#else
285#define PIXIS_BASE_PHYS PIXIS_BASE
286#endif
287
288#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
289#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7)
290
291#define PIXIS_LBMAP_SWITCH 7
292#define PIXIS_LBMAP_MASK 0xF0
293#define PIXIS_LBMAP_ALTBANK 0x20
294#define PIXIS_SPD 0x07
295#define PIXIS_SPD_SYSCLK_MASK 0x07
296#define PIXIS_ELBC_SPI_MASK 0xc0
297#define PIXIS_SPI 0x80
298
299#define CONFIG_SYS_INIT_RAM_LOCK
300#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
301#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
302
303#define CONFIG_SYS_GBL_DATA_OFFSET \
304 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
305#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
306
307#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
308#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
309
310
311
312
313#if defined(CONFIG_SPL_BUILD)
314#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
315#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
316#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
317#define CONFIG_SYS_L2_SIZE (256 << 10)
318#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
319#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
320#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
321#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
322#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
323#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
324#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
325#elif defined(CONFIG_NAND)
326#ifdef CONFIG_TPL_BUILD
327#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
328#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
329#define CONFIG_SYS_L2_SIZE (256 << 10)
330#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
331#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
332#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
333#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
334#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
335#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
336#else
337#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
338#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
339#define CONFIG_SYS_L2_SIZE (256 << 10)
340#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
341#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
342#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
343#endif
344#endif
345#endif
346
347
348
349
350#define CONFIG_CONS_INDEX 1
351#define CONFIG_SYS_NS16550_SERIAL
352#define CONFIG_SYS_NS16550_REG_SIZE 1
353#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
354#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
355#define CONFIG_NS16550_MIN_FUNCTIONS
356#endif
357
358#define CONFIG_SYS_BAUDRATE_TABLE \
359 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
360
361#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
362#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
363
364
365
366#ifdef CONFIG_FSL_DIU_FB
367#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
368#define CONFIG_CMD_BMP
369#define CONFIG_VIDEO_LOGO
370#define CONFIG_VIDEO_BMP_LOGO
371#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
372
373
374
375
376#undef CONFIG_SYS_FLASH_EMPTY_INFO
377#endif
378
379#ifndef CONFIG_FSL_DIU_FB
380#endif
381
382#ifdef CONFIG_ATI
383#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
384#define CONFIG_BIOSEMU
385#define CONFIG_ATI_RADEON_FB
386#define CONFIG_VIDEO_LOGO
387#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
388#endif
389
390
391#define CONFIG_SYS_I2C
392#define CONFIG_SYS_I2C_FSL
393#define CONFIG_SYS_FSL_I2C_SPEED 400000
394#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
395#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
396#define CONFIG_SYS_FSL_I2C2_SPEED 400000
397#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
398#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
399#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
400
401
402
403
404#define CONFIG_ID_EEPROM
405#define CONFIG_SYS_I2C_EEPROM_NXID
406#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
407#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
408#define CONFIG_SYS_EEPROM_BUS_NUM 1
409
410
411
412
413
414#define CONFIG_HARD_SPI
415
416#define CONFIG_SF_DEFAULT_SPEED 10000000
417#define CONFIG_SF_DEFAULT_MODE 0
418
419
420
421
422
423
424
425#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
426#ifdef CONFIG_PHYS_64BIT
427#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
428#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
429#else
430#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
431#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
432#endif
433#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
434#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
435#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
436#ifdef CONFIG_PHYS_64BIT
437#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
438#else
439#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
440#endif
441#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
442
443
444#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
445#ifdef CONFIG_PHYS_64BIT
446#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
447#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
448#else
449#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
450#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
451#endif
452#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000
453#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
454#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
455#ifdef CONFIG_PHYS_64BIT
456#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
457#else
458#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
459#endif
460#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
461
462
463#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
464#ifdef CONFIG_PHYS_64BIT
465#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
466#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
467#else
468#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
469#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
470#endif
471#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000
472#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
473#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
474#ifdef CONFIG_PHYS_64BIT
475#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
476#else
477#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
478#endif
479#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
480
481#ifdef CONFIG_PCI
482#define CONFIG_PCI_INDIRECT_BRIDGE
483#define CONFIG_PCI_SCAN_SHOW
484#endif
485
486
487#define CONFIG_LIBATA
488#define CONFIG_FSL_SATA
489#define CONFIG_FSL_SATA_V2
490
491#define CONFIG_SYS_SATA_MAX_DEVICE 2
492#define CONFIG_SATA1
493#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
494#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
495#define CONFIG_SATA2
496#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
497#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
498
499#ifdef CONFIG_FSL_SATA
500#define CONFIG_LBA48
501#define CONFIG_CMD_SATA
502#endif
503
504#ifdef CONFIG_MMC
505#define CONFIG_FSL_ESDHC
506#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
507#endif
508
509#define CONFIG_TSEC_ENET
510#ifdef CONFIG_TSEC_ENET
511
512#define CONFIG_TSECV2
513
514#define CONFIG_MII
515#define CONFIG_TSEC1 1
516#define CONFIG_TSEC1_NAME "eTSEC1"
517#define CONFIG_TSEC2 1
518#define CONFIG_TSEC2_NAME "eTSEC2"
519
520#define TSEC1_PHY_ADDR 1
521#define TSEC2_PHY_ADDR 2
522
523#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
524#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
525
526#define TSEC1_PHYIDX 0
527#define TSEC2_PHYIDX 0
528
529#define CONFIG_ETHPRIME "eTSEC1"
530
531#define CONFIG_PHY_GIGE
532#endif
533
534
535
536
537#define CONFIG_MTD_DEVICE
538#define CONFIG_MTD_PARTITIONS
539#define CONFIG_CMD_MTDPARTS
540#define CONFIG_FLASH_CFI_MTD
541#ifdef CONFIG_PHYS_64BIT
542#define MTDIDS_DEFAULT "nor0=fe8000000.nor"
543#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:48m(ramdisk)," \
544 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \
545 "512k(dtb),768k(u-boot)"
546#else
547#define MTDIDS_DEFAULT "nor0=e8000000.nor"
548#define MTDPARTS_DEFAULT "mtdparts=e8000000.nor:48m(ramdisk)," \
549 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \
550 "512k(dtb),768k(u-boot)"
551#endif
552
553
554
555
556#ifdef CONFIG_SPIFLASH
557#define CONFIG_ENV_IS_IN_SPI_FLASH
558#define CONFIG_ENV_SPI_BUS 0
559#define CONFIG_ENV_SPI_CS 0
560#define CONFIG_ENV_SPI_MAX_HZ 10000000
561#define CONFIG_ENV_SPI_MODE 0
562#define CONFIG_ENV_SIZE 0x2000
563#define CONFIG_ENV_OFFSET 0x100000
564#define CONFIG_ENV_SECT_SIZE 0x10000
565#elif defined(CONFIG_SDCARD)
566#define CONFIG_ENV_IS_IN_MMC
567#define CONFIG_FSL_FIXED_MMC_LOCATION
568#define CONFIG_ENV_SIZE 0x2000
569#define CONFIG_SYS_MMC_ENV_DEV 0
570#elif defined(CONFIG_NAND)
571#ifdef CONFIG_TPL_BUILD
572#define CONFIG_ENV_SIZE 0x2000
573#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
574#else
575#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
576#endif
577#define CONFIG_ENV_IS_IN_NAND
578#define CONFIG_ENV_OFFSET (1024 * 1024)
579#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
580#elif defined(CONFIG_SYS_RAMBOOT)
581#define CONFIG_ENV_IS_NOWHERE
582#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
583#define CONFIG_ENV_SIZE 0x2000
584#else
585#define CONFIG_ENV_IS_IN_FLASH
586#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
587#define CONFIG_ENV_SIZE 0x2000
588#define CONFIG_ENV_SECT_SIZE 0x20000
589#endif
590
591#define CONFIG_LOADS_ECHO
592#define CONFIG_SYS_LOADS_BAUD_CHANGE
593
594
595
596
597#define CONFIG_CMD_ERRATA
598#define CONFIG_CMD_IRQ
599#define CONFIG_CMD_REGINFO
600
601#ifdef CONFIG_PCI
602#define CONFIG_CMD_PCI
603#endif
604
605
606
607
608#define CONFIG_HAS_FSL_DR_USB
609#ifdef CONFIG_HAS_FSL_DR_USB
610#define CONFIG_USB_EHCI
611
612#ifdef CONFIG_USB_EHCI
613#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
614#define CONFIG_USB_EHCI_FSL
615#endif
616#endif
617
618
619
620
621#define CONFIG_SYS_LONGHELP
622#define CONFIG_CMDLINE_EDITING
623#define CONFIG_AUTO_COMPLETE
624#define CONFIG_SYS_LOAD_ADDR 0x2000000
625#ifdef CONFIG_CMD_KGDB
626#define CONFIG_SYS_CBSIZE 1024
627#else
628#define CONFIG_SYS_CBSIZE 256
629#endif
630
631#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
632#define CONFIG_SYS_MAXARGS 16
633#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
634
635
636
637
638
639
640#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
641#define CONFIG_SYS_BOOTM_LEN (64 << 20)
642
643#ifdef CONFIG_CMD_KGDB
644#define CONFIG_KGDB_BAUDRATE 230400
645#endif
646
647
648
649
650
651#define CONFIG_HOSTNAME p1022ds
652#define CONFIG_ROOTPATH "/opt/nfsroot"
653#define CONFIG_BOOTFILE "uImage"
654#define CONFIG_UBOOTPATH u-boot.bin
655
656#define CONFIG_LOADADDR 1000000
657
658
659#define CONFIG_BAUDRATE 115200
660
661#define CONFIG_EXTRA_ENV_SETTINGS \
662 "netdev=eth0\0" \
663 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
664 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
665 "tftpflash=tftpboot $loadaddr $uboot && " \
666 "protect off $ubootaddr +$filesize && " \
667 "erase $ubootaddr +$filesize && " \
668 "cp.b $loadaddr $ubootaddr $filesize && " \
669 "protect on $ubootaddr +$filesize && " \
670 "cmp.b $loadaddr $ubootaddr $filesize\0" \
671 "consoledev=ttyS0\0" \
672 "ramdiskaddr=2000000\0" \
673 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
674 "fdtaddr=1e00000\0" \
675 "fdtfile=p1022ds.dtb\0" \
676 "bdev=sda3\0" \
677 "hwconfig=esdhc;audclk:12\0"
678
679#define CONFIG_HDBOOT \
680 "setenv bootargs root=/dev/$bdev rw " \
681 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
682 "tftp $loadaddr $bootfile;" \
683 "tftp $fdtaddr $fdtfile;" \
684 "bootm $loadaddr - $fdtaddr"
685
686#define CONFIG_NFSBOOTCOMMAND \
687 "setenv bootargs root=/dev/nfs rw " \
688 "nfsroot=$serverip:$rootpath " \
689 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
690 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
691 "tftp $loadaddr $bootfile;" \
692 "tftp $fdtaddr $fdtfile;" \
693 "bootm $loadaddr - $fdtaddr"
694
695#define CONFIG_RAMBOOTCOMMAND \
696 "setenv bootargs root=/dev/ram rw " \
697 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
698 "tftp $ramdiskaddr $ramdiskfile;" \
699 "tftp $loadaddr $bootfile;" \
700 "tftp $fdtaddr $fdtfile;" \
701 "bootm $loadaddr $ramdiskaddr $fdtaddr"
702
703#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
704
705#endif
706