1/* 2 * (C) Copyright 2003 3 * Denis Peter d.peter@mpl.ch 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* 9 * File: PATI.h 10 */ 11 12#ifndef __CONFIG_H 13#define __CONFIG_H 14 15/* 16 * High Level Configuration Options 17 */ 18 19#define CONFIG_MPC555 1 /* This is an MPC555 CPU */ 20#define CONFIG_PATI 1 /* ...On a PATI board */ 21 22#define CONFIG_SYS_TEXT_BASE 0xFFF00000 23 24/* Serial Console Configuration */ 25#define CONFIG_5xx_CONS_SCI1 26#undef CONFIG_5xx_CONS_SCI2 27 28#define CONFIG_BAUDRATE 9600 29 30/* 31 * BOOTP options 32 */ 33#define CONFIG_BOOTP_BOOTFILESIZE 34#define CONFIG_BOOTP_BOOTPATH 35#define CONFIG_BOOTP_GATEWAY 36#define CONFIG_BOOTP_HOSTNAME 37 38/* 39 * Command line configuration. 40 */ 41#define CONFIG_CMD_REGINFO 42#define CONFIG_CMD_REGINFO 43#define CONFIG_CMD_BSP 44#define CONFIG_CMD_EEPROM 45#define CONFIG_CMD_IRQ 46 47#define CONFIG_BOOTCOMMAND "" /* autoboot command */ 48 49#define CONFIG_BOOTARGS "" /* */ 50 51#define CONFIG_WATCHDOG /* turn on platform specific watchdog */ 52 53#define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */ 54 55/* 56 * Miscellaneous configurable options 57 */ 58#define CONFIG_PREBOOT 59 60#define CONFIG_SYS_LONGHELP /* undef to save memory */ 61#if defined(CONFIG_CMD_KGDB) 62#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 63#else 64#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 65#endif 66#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 67#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 68#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 69 70#define CONFIG_SYS_MEMTEST_START 0x00010000 /* memtest works on */ 71#define CONFIG_SYS_MEMTEST_END 0x00A00000 /* 10 MB in SRAM */ 72 73#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 74 75#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 } 76 77/*********************************************************************** 78 * Last Stage Init 79 ***********************************************************************/ 80#define CONFIG_LAST_STAGE_INIT 81 82/* 83 * Low Level Configuration Settings 84 */ 85 86/* 87 * Internal Memory Mapped (This is not the IMMR content) 88 */ 89#define CONFIG_SYS_IMMR 0x01C00000 /* Physical start adress of internal memory map */ 90 91/* 92 * Definitions for initial stack pointer and data area 93 */ 94#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */ 95#define CONFIG_SYS_INIT_RAM_SIZE (CONFIG_SYS_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */ 96#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_RAM_ADDR) - GENERATED_GBL_DATA_SIZE) /* Offset from the beginning of ram */ 97#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_IMMR + 0x03fa000) /* Physical start adress of inital stack */ 98/* 99 * Start addresses for the final memory configuration 100 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 101 */ 102#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */ 103#define CONFIG_SYS_FLASH_BASE 0xffC00000 /* External flash */ 104#define PCI_BASE 0x03000000 /* PCI Base (CS2) */ 105#define PCI_CONFIG_BASE 0x04000000 /* PCI & PLD (CS3) */ 106#define PLD_CONFIG_BASE 0x04001000 /* PLD (CS3) */ 107 108#define CONFIG_SYS_MONITOR_BASE 0xFFF00000 109/* CONFIG_SYS_FLASH_BASE */ /* CONFIG_SYS_TEXT_BASE is defined in the board config.mk file. */ 110 /* This adress is given to the linker with -Ttext to */ 111 /* locate the text section at this adress. */ 112#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 192 kB for Monitor */ 113#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 114 115#define CONFIG_SYS_RESET_ADDRESS (PLD_CONFIG_BASE + 0x10) /* Adress which causes reset */ 116 117/* 118 * For booting Linux, the board info and command line data 119 * have to be in the first 8 MB of memory, since this is 120 * the maximum mapped by the Linux kernel during initialization. 121 */ 122#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 123 124/*----------------------------------------------------------------------- 125 * FLASH organization 126 *----------------------------------------------------------------------- 127 * 128 */ 129 130#define CONFIG_SYS_FLASH_PROTECTION 131#define CONFIG_SYS_FLASH_EMPTY_INFO 132 133#define CONFIG_SYS_FLASH_CFI 134#define CONFIG_FLASH_CFI_DRIVER 135 136#define CONFIG_FLASH_SHOW_PROGRESS 45 137 138#define CONFIG_SYS_MAX_FLASH_BANKS 1 139#define CONFIG_SYS_MAX_FLASH_SECT 128 140 141#define CONFIG_ENV_IS_IN_EEPROM 142#ifdef CONFIG_ENV_IS_IN_EEPROM 143#define CONFIG_ENV_OFFSET 0 144#define CONFIG_ENV_SIZE 2048 145#endif 146 147#undef CONFIG_ENV_IS_IN_FLASH 148#ifdef CONFIG_ENV_IS_IN_FLASH 149#define CONFIG_ENV_SIZE 0x00002000 /* Set whole sector as env */ 150#define CONFIG_ENV_OFFSET ((0 - CONFIG_SYS_FLASH_BASE) - CONFIG_ENV_SIZE) /* Environment starts at this adress */ 151#endif 152 153#define CONFIG_SPI 1 154#define CONFIG_SYS_SPI_CS_USED 0x09 /* CS0 and CS3 are used */ 155#define CONFIG_SYS_SPI_CS_BASE 0x08 /* CS3 is active low */ 156#define CONFIG_SYS_SPI_CS_ACT 0x00 /* CS3 is active low */ 157/*----------------------------------------------------------------------- 158 * SYPCR - System Protection Control 159 * SYPCR can only be written once after reset! 160 *----------------------------------------------------------------------- 161 * SW Watchdog freeze 162 */ 163#undef CONFIG_WATCHDOG 164#if defined(CONFIG_WATCHDOG) 165#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 166 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 167#else 168#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 169 SYPCR_SWP) 170#endif /* CONFIG_WATCHDOG */ 171 172/*----------------------------------------------------------------------- 173 * TBSCR - Time Base Status and Control 174 *----------------------------------------------------------------------- 175 * Clear Reference Interrupt Status, Timebase freezing enabled 176 */ 177#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 178 179/*----------------------------------------------------------------------- 180 * PISCR - Periodic Interrupt Status and Control 181 *----------------------------------------------------------------------- 182 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 183 */ 184#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 185 186/*----------------------------------------------------------------------- 187 * SCCR - System Clock and reset Control Register 188 *----------------------------------------------------------------------- 189 * Set clock output, timebase and RTC source and divider, 190 * power management and some other internal clocks 191 */ 192#define SCCR_MASK SCCR_EBDF00 193#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \ 194 SCCR_COM01 | SCCR_DFNL000 | SCCR_DFNH000) 195 196/*----------------------------------------------------------------------- 197 * SIUMCR - SIU Module Configuration 198 *----------------------------------------------------------------------- 199 * Data show cycle 200 */ 201#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */ 202 203/*----------------------------------------------------------------------- 204 * PLPRCR - PLL, Low-Power, and Reset Control Register 205 *----------------------------------------------------------------------- 206 * Set all bits to 40 Mhz 207 * 208 */ 209#define CONFIG_SYS_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */ 210 211#define CONFIG_SYS_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0) 212 213/*----------------------------------------------------------------------- 214 * UMCR - UIMB Module Configuration Register 215 *----------------------------------------------------------------------- 216 * 217 */ 218#define CONFIG_SYS_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */ 219 220/*----------------------------------------------------------------------- 221 * ICTRL - I-Bus Support Control Register 222 */ 223#define CONFIG_SYS_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */ 224 225/*----------------------------------------------------------------------- 226 * USIU - Memory Controller Register 227 *----------------------------------------------------------------------- 228 */ 229#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA) 230#define CONFIG_SYS_OR0_PRELIM (0xffc00000) /* SCY is not used if external TA is set */ 231/* SDRAM */ 232#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA) 233#define CONFIG_SYS_OR1_PRELIM (OR_ADDR_MK_FF) /* SCY is not used if external TA is set */ 234/* PCI */ 235#define CONFIG_SYS_BR2_PRELIM (PCI_BASE | BR_V | BR_PS_32 | BR_SETA) 236#define CONFIG_SYS_OR2_PRELIM (OR_ADDR_MK_FF) 237/* config registers: */ 238#define CONFIG_SYS_BR3_PRELIM (PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA) 239#define CONFIG_SYS_OR3_PRELIM (0xffff0000) 240 241#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* We don't realign the flash */ 242 243/*----------------------------------------------------------------------- 244 * DER - Timer Decrementer 245 *----------------------------------------------------------------------- 246 * Initialise to zero 247 */ 248#define CONFIG_SYS_DER 0x00000000 249 250#endif /* __CONFIG_H */ 251