LXR uboot/include/configs/PMC440.h

   1/*
   2 * (C) Copyright 2007-2008
   3 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
   4 * Based on the sequoia configuration file.
   5 *
   6 * (C) Copyright 2006-2007
   7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
   8 *
   9 * (C) Copyright 2006
  10 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
  11 * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
  12 *
  13 * SPDX-License-Identifier:     GPL-2.0+
  14 */
  15
  16/************************************************************************
  17 * PMC440.h - configuration for esd PMC440 boards
  18 ***********************************************************************/
  19#ifndef __CONFIG_H
  20#define __CONFIG_H
  21
  22/*-----------------------------------------------------------------------
  23 * High Level Configuration Options
  24 *----------------------------------------------------------------------*/
  25#define CONFIG_440EPX           1       /* Specific PPC440EPx   */
  26#define CONFIG_440              1       /* ... PPC440 family    */
  27
  28#ifndef CONFIG_SYS_TEXT_BASE
  29#define CONFIG_SYS_TEXT_BASE    0xFFF90000
  30#endif
  31
  32#define CONFIG_SYS_CLK_FREQ     33333400
  33
  34#if 0 /* temporary disabled because OS/9 does not like dcache on startup */
  35#define CONFIG_4xx_DCACHE               /* enable dcache        */
  36#endif
  37
  38#define CONFIG_MISC_INIT_F      1
  39#define CONFIG_MISC_INIT_R      1       /* Call misc_init_r     */
  40#define CONFIG_BOARD_TYPES      1       /* support board types  */
  41/*-----------------------------------------------------------------------
  42 * Base addresses -- Note these are effective addresses where the
  43 * actual resources get mapped (not physical addresses)
  44 *----------------------------------------------------------------------*/
  45#define CONFIG_SYS_MONITOR_LEN          (~(CONFIG_SYS_TEXT_BASE) + 1)
  46#define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserve 256 kB for malloc()  */
  47
  48#define CONFIG_PRAM             0       /* use pram variable to overwrite */
  49
  50#define CONFIG_SYS_BOOT_BASE_ADDR       0xf0000000
  51#define CONFIG_SYS_SDRAM_BASE           0x00000000      /* _must_ be 0          */
  52#define CONFIG_SYS_FLASH_BASE           0xfc000000      /* start of FLASH       */
  53#define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
  54#define CONFIG_SYS_NAND_ADDR            0xd0000000      /* NAND Flash           */
  55#define CONFIG_SYS_OCM_BASE             0xe0010000      /* ocm                  */
  56#define CONFIG_SYS_OCM_DATA_ADDR        CONFIG_SYS_OCM_BASE
  57#define CONFIG_SYS_PCI_BASE             0xe0000000      /* Internal PCI regs    */
  58#define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped pci memory    */
  59#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE  + 0x10000000
  60#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
  61#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
  62#define CONFIG_SYS_PCI_MEMSIZE          0x80000000      /* 2GB! */
  63
  64#define CONFIG_SYS_USB2D0_BASE          0xe0000100
  65#define CONFIG_SYS_USB_DEVICE           0xe0000000
  66#define CONFIG_SYS_USB_HOST             0xe0000400
  67#define CONFIG_SYS_FPGA_BASE0           0xef000000      /* 32 bit */
  68#define CONFIG_SYS_FPGA_BASE1           0xef100000      /* 16 bit */
  69#define CONFIG_SYS_RESET_BASE           0xef200000
  70
  71/*-----------------------------------------------------------------------
  72 * Initial RAM & stack pointer
  73 *----------------------------------------------------------------------*/
  74/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache     */
  75#define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_BASE     /* OCM                  */
  76#define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)
  77#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  78#define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
  79
  80/*-----------------------------------------------------------------------
  81 * Serial Port
  82 *----------------------------------------------------------------------*/
  83#define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  84#define CONFIG_SYS_NS16550_SERIAL
  85#define CONFIG_SYS_NS16550_REG_SIZE     1
  86#define CONFIG_SYS_NS16550_CLK          get_serial_clock()
  87#undef CONFIG_SYS_EXT_SERIAL_CLOCK
  88#define CONFIG_BAUDRATE         115200
  89
  90#define CONFIG_SYS_BAUDRATE_TABLE                                               \
  91        {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  92
  93/*-----------------------------------------------------------------------
  94 * Environment
  95 *----------------------------------------------------------------------*/
  96#define CONFIG_ENV_IS_IN_EEPROM 1       /* use FLASH for environment vars */
  97
  98/*-----------------------------------------------------------------------
  99 * RTC
 100 *----------------------------------------------------------------------*/
 101#define CONFIG_RTC_RX8025
 102
 103/*-----------------------------------------------------------------------
 104 * FLASH related
 105 *----------------------------------------------------------------------*/
 106#define CONFIG_SYS_FLASH_CFI            /* The flash is CFI compatible  */
 107#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver        */
 108
 109#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 110
 111#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 112#define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
 113
 114#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 115#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 116
 117#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 118#define CONFIG_SYS_FLASH_PROTECTION     1       /* use hardware flash protection        */
 119
 120#define CONFIG_SYS_FLASH_EMPTY_INFO     /* print 'E' for empty sector on flinfo */
 121#define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash        */
 122
 123#ifdef CONFIG_ENV_IS_IN_FLASH
 124#define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector          */
 125#define CONFIG_ENV_ADDR         ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 126#define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector     */
 127
 128/* Address and size of Redundant Environment Sector     */
 129#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 130#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 131#endif
 132
 133#ifdef CONFIG_ENV_IS_IN_EEPROM
 134#define CONFIG_I2C_ENV_EEPROM_BUS       0
 135#define CONFIG_ENV_OFFSET               0       /* environment starts at the beginning of the EEPROM */
 136#define CONFIG_ENV_SIZE         0x1000  /* 4096 bytes may be used for env vars */
 137#endif
 138
 139/*-----------------------------------------------------------------------
 140 * DDR SDRAM
 141 *----------------------------------------------------------------------*/
 142#define CONFIG_DDR_DATA_EYE     /* use DDR2 optimization        */
 143#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
 144                                                  /* 440EPx errata CHIP 11 */
 145
 146/*-----------------------------------------------------------------------
 147 * I2C
 148 *----------------------------------------------------------------------*/
 149#define CONFIG_SYS_I2C
 150#define CONFIG_SYS_I2C_PPC4XX
 151#define CONFIG_SYS_I2C_PPC4XX_CH0
 152#define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 153#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 154#define CONFIG_SYS_I2C_PPC4XX_CH1
 155#define CONFIG_SYS_I2C_PPC4XX_SPEED_1           400000
 156#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1           0x7F
 157
 158#define CONFIG_SYS_I2C_EEPROM_ADDR              0x54
 159#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 160#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5
 161#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 162#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x01
 163
 164#define CONFIG_SYS_EEPROM_WREN                  1
 165#define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR 0x52
 166
 167/*
 168 * standard dtt sensor configuration - bottom bit will determine local or
 169 * remote sensor of the TMP401
 170 */
 171#define CONFIG_DTT_SENSORS              { 0, 1 }
 172
 173/*
 174 * The PMC440 uses a TI TMP401 temperature sensor. This part
 175 * is basically compatible to the ADM1021 that is supported
 176 * by U-Boot.
 177 *
 178 * - i2c addr 0x4c
 179 * - conversion rate 0x02 = 0.25 conversions/second
 180 * - ALERT ouput disabled
 181 * - local temp sensor enabled, min set to 0 deg, max set to 70 deg
 182 * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
 183 */
 184#define CONFIG_DTT_ADM1021
 185#define CONFIG_SYS_DTT_ADM1021          { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
 186
 187#define CONFIG_PREBOOT          "echo Add \\\"run fpga\\\" and "        \
 188                                "\\\"painit\\\" to preboot command"
 189
 190#undef  CONFIG_BOOTARGS
 191
 192/* Setup some board specific values for the default environment variables */
 193#define CONFIG_HOSTNAME         pmc440
 194#define CONFIG_SYS_BOOTFILE     "bootfile=/tftpboot/pmc440/uImage\0"
 195#define CONFIG_SYS_ROOTPATH     "rootpath=/opt/eldk/ppc_4xxFP\0"
 196
 197#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 198        CONFIG_SYS_BOOTFILE                                             \
 199        CONFIG_SYS_ROOTPATH                                             \
 200        "fdt_file=/tftpboot/pmc440/pmc440.dtb\0"                        \
 201        "netdev=eth0\0"                                                 \
 202        "ethrotate=no\0"                                                \
 203        "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 204        "nfsroot=${serverip}:${rootpath}\0"                             \
 205        "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 206        "addip=setenv bootargs ${bootargs} "                            \
 207                "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 208                ":${hostname}:${netdev}:off panic=1\0"                  \
 209        "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
 210        "addmisc=setenv bootargs ${bootargs} mem=${mem}\0"              \
 211        "nandargs=setenv bootargs root=/dev/mtdblock6 rootfstype=jffs2 rw\0" \
 212        "nand_boot_fdt=run nandargs addip addtty addmisc;"              \
 213                "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 214        "net_nfs_fdt=tftp ${kernel_addr_r} ${bootfile};"                \
 215                "tftp  ${fdt_addr_r} ${fdt_file};"                      \
 216                "run nfsargs addip addtty addmisc;"                     \
 217                "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 218        "kernel_addr=ffc00000\0"                                        \
 219        "kernel_addr_r=200000\0"                                        \
 220        "fpga_addr=fff00000\0"                                          \
 221        "fdt_addr=fff80000\0"                                           \
 222        "fdt_addr_r=800000\0"                                           \
 223        "fpga=fpga loadb 0 ${fpga_addr}\0"                              \
 224        "load=tftp 200000 /tftpboot/pmc440/u-boot.bin\0"                \
 225        "update=protect off fff90000 ffffffff;era fff90000 ffffffff;"   \
 226                "cp.b 200000 fff90000 70000\0"                          \
 227        ""
 228
 229
 230#define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 231#define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 232
 233#define CONFIG_PPC4xx_EMAC
 234#define CONFIG_IBM_EMAC4_V4     1
 235#define CONFIG_MII              1       /* MII PHY management           */
 236#define CONFIG_PHY_ADDR         0       /* PHY address, See schematics  */
 237
 238#define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 239
 240#define CONFIG_HAS_ETH0
 241#define CONFIG_SYS_RX_ETH_BUFFER        32      /* Number of ethernet rx buffers & descriptors */
 242
 243#define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 244#define CONFIG_PHY1_ADDR        1
 245#define CONFIG_RESET_PHY_R      1
 246
 247/* USB */
 248#define CONFIG_USB_OHCI_NEW
 249#define CONFIG_SYS_OHCI_BE_CONTROLLER
 250
 251#define CONFIG_SYS_USB_OHCI_BOARD_INIT 1
 252#define CONFIG_SYS_USB_OHCI_CPU_INIT    1
 253#define CONFIG_SYS_USB_OHCI_REGS_BASE   CONFIG_SYS_USB_HOST
 254#define CONFIG_SYS_USB_OHCI_SLOT_NAME   "ppc440"
 255#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 256
 257/* Comment this out to enable USB 1.1 device */
 258#define USB_2_0_DEVICE
 259
 260/* Partitions */
 261
 262#define CONFIG_CMD_BSP
 263#define CONFIG_CMD_DATE
 264#define CONFIG_CMD_DTT
 265#define CONFIG_CMD_EEPROM
 266#define CONFIG_CMD_NAND
 267#define CONFIG_CMD_PCI
 268#define CONFIG_CMD_REGINFO
 269
 270/* POST support */
 271#define CONFIG_POST             (CONFIG_SYS_POST_MEMORY |       \
 272                                 CONFIG_SYS_POST_CPU    |       \
 273                                 CONFIG_SYS_POST_UART   |       \
 274                                 CONFIG_SYS_POST_I2C    |       \
 275                                 CONFIG_SYS_POST_CACHE  |       \
 276                                 CONFIG_SYS_POST_FPU    |       \
 277                                 CONFIG_SYS_POST_ETHER  |       \
 278                                 CONFIG_SYS_POST_SPR)
 279
 280#define CONFIG_LOGBUFFER
 281#define CONFIG_SYS_POST_CACHE_ADDR      0x7fff0000      /* free virtual address     */
 282
 283#define CONFIG_SUPPORT_VFAT
 284
 285/*-----------------------------------------------------------------------
 286 * Miscellaneous configurable options
 287 *----------------------------------------------------------------------*/
 288#define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 289#if defined(CONFIG_CMD_KGDB)
 290#define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 291#else
 292#define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 293#endif
 294#define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 295#define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 296#define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 297
 298#define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on          */
 299#define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM       */
 300
 301#define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address      */
 302#define CONFIG_SYS_EXTBDINFO            1       /* To use extended board_into (bd_t) */
 303
 304#define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 305#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 306
 307/*-----------------------------------------------------------------------
 308 * PCI stuff
 309 *----------------------------------------------------------------------*/
 310/* General PCI */
 311#define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 312#define CONFIG_SYS_PCI_CACHE_LINE_SIZE  0       /* to avoid problems with PNP   */
 313#define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup  */
 314#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
 315
 316/* Board-specific PCI */
 317#define CONFIG_SYS_PCI_TARGET_INIT
 318#define CONFIG_SYS_PCI_MASTER_INIT
 319#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
 320
 321#define CONFIG_PCI_BOOTDELAY 0
 322
 323/* PCI identification */
 324#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE   /* PCI Vendor ID: esd gmbh      */
 325#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x0441      /* PCI Device ID: Non-Monarch */
 326#define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x0440 /* PCI Device ID: Monarch */
 327/* for weak __pci_target_init() */
 328#define CONFIG_SYS_PCI_SUBSYS_ID        CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
 329#define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH     PCI_CLASS_PROCESSOR_POWERPC
 330#define CONFIG_SYS_PCI_CLASSCODE_MONARCH        PCI_CLASS_BRIDGE_HOST
 331
 332/*
 333 * For booting Linux, the board info and command line data
 334 * have to be in the first 8 MB of memory, since this is
 335 * the maximum mapped by the Linux kernel during initialization.
 336 */
 337#define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 338
 339/*-----------------------------------------------------------------------
 340 * FPGA stuff
 341 *----------------------------------------------------------------------*/
 342#define CONFIG_FPGA
 343#define CONFIG_FPGA_XILINX
 344#define CONFIG_FPGA_SPARTAN2
 345#define CONFIG_FPGA_SPARTAN3
 346
 347#define CONFIG_FPGA_COUNT       2
 348/*-----------------------------------------------------------------------
 349 * External Bus Controller (EBC) Setup
 350 *----------------------------------------------------------------------*/
 351
 352/*
 353 * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
 354 */
 355#define CONFIG_SYS_NAND_CS              2       /* NAND chip connected to CSx   */
 356
 357/* Memory Bank 0 (NOR-FLASH) initialization */
 358#define CONFIG_SYS_EBC_PB0AP            0x03017200
 359#define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_FLASH_BASE | 0xda000)
 360
 361/* Memory Bank 2 (NAND-FLASH) initialization */
 362#define CONFIG_SYS_EBC_PB2AP            0x018003c0
 363#define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_NAND_ADDR | 0x1c000)
 364
 365/* Memory Bank 1 (RESET) initialization */
 366#define CONFIG_SYS_EBC_PB1AP            0x7f817200 /* 0x03017200 */
 367#define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_RESET_BASE | 0x1c000)
 368
 369/* Memory Bank 4 (FPGA / 32Bit) initialization */
 370#define CONFIG_SYS_EBC_PB4AP            0x03840f40      /* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */
 371#define CONFIG_SYS_EBC_PB4CR            (CONFIG_SYS_FPGA_BASE0 | 0x1c000)       /* BS=1M,BU=R/W,BW=32bit */
 372
 373/* Memory Bank 5 (FPGA / 16Bit) initialization */
 374#define CONFIG_SYS_EBC_PB5AP            0x03840f40      /* BME=0,TWT=3,CSN=1,TH=0,RE=1,SOR=0,BEM=1 */
 375#define CONFIG_SYS_EBC_PB5CR            (CONFIG_SYS_FPGA_BASE1 | 0x1a000)       /* BS=1M,BU=R/W,BW=16bit */
 376
 377/*-----------------------------------------------------------------------
 378 * NAND FLASH
 379 *----------------------------------------------------------------------*/
 380#define CONFIG_SYS_MAX_NAND_DEVICE      1
 381#define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
 382#define CONFIG_SYS_NAND_SELECT_DEVICE   1 /* nand driver supports mutipl. chips */
 383
 384#if defined(CONFIG_CMD_KGDB)
 385#define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 386#endif
 387
 388#endif /* __CONFIG_H */
 389