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11#ifndef __T1024QDS_H
12#define __T1024QDS_H
13
14
15#define CONFIG_SYS_BOOK3E_HV
16#define CONFIG_MP
17#define CONFIG_ENABLE_36BIT_PHYS
18
19#ifdef CONFIG_PHYS_64BIT
20#define CONFIG_ADDR_MAP 1
21#define CONFIG_SYS_NUM_ADDR_MAP 64
22#endif
23
24#define CONFIG_SYS_FSL_CPC
25#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
26
27#define CONFIG_ENV_OVERWRITE
28
29#define CONFIG_DEEP_SLEEP
30
31#ifdef CONFIG_RAMBOOT_PBL
32#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
33#define CONFIG_SPL_FLUSH_IMAGE
34#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
35#define CONFIG_SYS_TEXT_BASE 0x00201000
36#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
37#define CONFIG_SPL_PAD_TO 0x40000
38#define CONFIG_SPL_MAX_SIZE 0x28000
39#define RESET_VECTOR_OFFSET 0x27FFC
40#define BOOT_PAGE_OFFSET 0x27000
41#ifdef CONFIG_SPL_BUILD
42#define CONFIG_SPL_SKIP_RELOCATE
43#define CONFIG_SPL_COMMON_INIT_DDR
44#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
45#endif
46
47#ifdef CONFIG_NAND
48#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
49#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
50#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
51#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
52#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
53#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg
54#define CONFIG_SPL_NAND_BOOT
55#endif
56
57#ifdef CONFIG_SPIFLASH
58#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
59#define CONFIG_SPL_SPI_FLASH_MINIMAL
60#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
61#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
62#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
63#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
64#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
65#ifndef CONFIG_SPL_BUILD
66#define CONFIG_SYS_MPC85XX_NO_RESETVEC
67#endif
68#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg
69#define CONFIG_SPL_SPI_BOOT
70#endif
71
72#ifdef CONFIG_SDCARD
73#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
74#define CONFIG_SPL_MMC_MINIMAL
75#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
76#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
77#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
78#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
79#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
80#ifndef CONFIG_SPL_BUILD
81#define CONFIG_SYS_MPC85XX_NO_RESETVEC
82#endif
83#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg
84#define CONFIG_SPL_MMC_BOOT
85#endif
86
87#endif
88
89#ifndef CONFIG_SYS_TEXT_BASE
90#define CONFIG_SYS_TEXT_BASE 0xeff40000
91#endif
92
93#ifndef CONFIG_RESET_VECTOR_ADDRESS
94#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
95#endif
96
97#ifdef CONFIG_MTD_NOR_FLASH
98#define CONFIG_FLASH_CFI_DRIVER
99#define CONFIG_SYS_FLASH_CFI
100#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
101#endif
102
103
104#define CONFIG_SRIO_PCIE_BOOT_MASTER
105
106
107
108
109#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
110#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000
111#ifdef CONFIG_PHYS_64BIT
112#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
113#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
114#else
115#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
116#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
117#endif
118
119
120
121
122#ifdef CONFIG_PHYS_64BIT
123#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
124#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
125#else
126#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
127#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
128#endif
129#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000
130
131#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
132#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001
133
134
135#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
136#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
137#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
138 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
139
140#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
141#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
142 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
143#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
144#endif
145
146#if defined(CONFIG_SPIFLASH)
147#define CONFIG_SYS_EXTRA_ENV_RELOC
148#define CONFIG_ENV_IS_IN_SPI_FLASH
149#define CONFIG_ENV_SPI_BUS 0
150#define CONFIG_ENV_SPI_CS 0
151#define CONFIG_ENV_SPI_MAX_HZ 10000000
152#define CONFIG_ENV_SPI_MODE 0
153#define CONFIG_ENV_SIZE 0x2000
154#define CONFIG_ENV_OFFSET 0x100000
155#define CONFIG_ENV_SECT_SIZE 0x10000
156#elif defined(CONFIG_SDCARD)
157#define CONFIG_SYS_EXTRA_ENV_RELOC
158#define CONFIG_ENV_IS_IN_MMC
159#define CONFIG_SYS_MMC_ENV_DEV 0
160#define CONFIG_ENV_SIZE 0x2000
161#define CONFIG_ENV_OFFSET (512 * 0x800)
162#elif defined(CONFIG_NAND)
163#define CONFIG_SYS_EXTRA_ENV_RELOC
164#define CONFIG_ENV_IS_IN_NAND
165#define CONFIG_ENV_SIZE 0x2000
166#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
167#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
168#define CONFIG_ENV_IS_IN_REMOTE
169#define CONFIG_ENV_ADDR 0xffe20000
170#define CONFIG_ENV_SIZE 0x2000
171#elif defined(CONFIG_ENV_IS_NOWHERE)
172#define CONFIG_ENV_SIZE 0x2000
173#else
174#define CONFIG_ENV_IS_IN_FLASH
175#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
176#define CONFIG_ENV_SIZE 0x2000
177#define CONFIG_ENV_SECT_SIZE 0x20000
178#endif
179
180#ifndef __ASSEMBLY__
181unsigned long get_board_sys_clk(void);
182unsigned long get_board_ddr_clk(void);
183#endif
184
185#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
186#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
187
188
189
190
191#define CONFIG_SYS_CACHE_STASHING
192#define CONFIG_BACKSIDE_L2_CACHE
193#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
194#define CONFIG_BTB
195#define CONFIG_DDR_ECC
196#ifdef CONFIG_DDR_ECC
197#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
198#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
199#endif
200
201#define CONFIG_SYS_MEMTEST_START 0x00200000
202#define CONFIG_SYS_MEMTEST_END 0x00400000
203#define CONFIG_SYS_ALT_MEMTEST
204#define CONFIG_PANIC_HANG
205
206
207
208
209#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
210#define CONFIG_SYS_L3_SIZE (256 << 10)
211#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
212#ifdef CONFIG_RAMBOOT_PBL
213#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
214#endif
215#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
216#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
217#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
218#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
219
220#ifdef CONFIG_PHYS_64BIT
221#define CONFIG_SYS_DCSRBAR 0xf0000000
222#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
223#endif
224
225
226#define CONFIG_ID_EEPROM
227#define CONFIG_SYS_I2C_EEPROM_NXID
228#define CONFIG_SYS_EEPROM_BUS_NUM 0
229#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
230#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
231#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
232#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
233
234
235
236
237#define CONFIG_VERY_BIG_RAM
238#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
239#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
240#define CONFIG_DIMM_SLOTS_PER_CTLR 1
241#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
242#define CONFIG_DDR_SPD
243
244#define CONFIG_SYS_SPD_BUS_NUM 0
245#define SPD_EEPROM_ADDRESS 0x51
246
247#define CONFIG_SYS_SDRAM_SIZE 4096
248
249
250
251
252#define CONFIG_SYS_FLASH_BASE 0xe0000000
253#ifdef CONFIG_PHYS_64BIT
254#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
255#else
256#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
257#endif
258
259#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
260#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
261 + 0x8000000) | \
262 CSPR_PORT_SIZE_16 | \
263 CSPR_MSEL_NOR | \
264 CSPR_V)
265#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
266#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
267 CSPR_PORT_SIZE_16 | \
268 CSPR_MSEL_NOR | \
269 CSPR_V)
270#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
271
272#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
273#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
274 FTIM0_NOR_TEADC(0x5) | \
275 FTIM0_NOR_TEAHC(0x5))
276#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
277 FTIM1_NOR_TRAD_NOR(0x1A) |\
278 FTIM1_NOR_TSEQRAD_NOR(0x13))
279#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
280 FTIM2_NOR_TCH(0x4) | \
281 FTIM2_NOR_TWPH(0x0E) | \
282 FTIM2_NOR_TWP(0x1c))
283#define CONFIG_SYS_NOR_FTIM3 0x0
284
285#define CONFIG_SYS_FLASH_QUIET_TEST
286#define CONFIG_FLASH_SHOW_PROGRESS 45
287
288#define CONFIG_SYS_MAX_FLASH_BANKS 2
289#define CONFIG_SYS_MAX_FLASH_SECT 1024
290#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
291#define CONFIG_SYS_FLASH_WRITE_TOUT 500
292
293#define CONFIG_SYS_FLASH_EMPTY_INFO
294#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
295 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
296#define CONFIG_FSL_QIXIS
297#define QIXIS_BASE 0xffdf0000
298#ifdef CONFIG_PHYS_64BIT
299#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
300#else
301#define QIXIS_BASE_PHYS QIXIS_BASE
302#endif
303#define QIXIS_LBMAP_SWITCH 0x06
304#define QIXIS_LBMAP_MASK 0x0f
305#define QIXIS_LBMAP_SHIFT 0
306#define QIXIS_LBMAP_DFLTBANK 0x00
307#define QIXIS_LBMAP_ALTBANK 0x04
308#define QIXIS_RST_CTL_RESET 0x31
309#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
310#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
311#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
312#define QIXIS_RST_FORCE_MEM 0x01
313
314#define CONFIG_SYS_CSPR3_EXT (0xf)
315#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
316 | CSPR_PORT_SIZE_8 \
317 | CSPR_MSEL_GPCM \
318 | CSPR_V)
319#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
320#define CONFIG_SYS_CSOR3 0x0
321
322#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
323 FTIM0_GPCM_TEADC(0x0e) | \
324 FTIM0_GPCM_TEAHC(0x0e))
325#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
326 FTIM1_GPCM_TRAD(0x3f))
327#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
328 FTIM2_GPCM_TCH(0x8) | \
329 FTIM2_GPCM_TWP(0x1f))
330#define CONFIG_SYS_CS3_FTIM3 0x0
331
332#define CONFIG_NAND_FSL_IFC
333#define CONFIG_SYS_NAND_BASE 0xff800000
334#ifdef CONFIG_PHYS_64BIT
335#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
336#else
337#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
338#endif
339#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
340#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
341 | CSPR_PORT_SIZE_8 \
342 | CSPR_MSEL_NAND \
343 | CSPR_V)
344#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
345
346#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
347 | CSOR_NAND_ECC_DEC_EN \
348 | CSOR_NAND_ECC_MODE_4 \
349 | CSOR_NAND_RAL_3 \
350 | CSOR_NAND_PGS_2K \
351 | CSOR_NAND_SPRZ_64 \
352 | CSOR_NAND_PB(64))
353
354#define CONFIG_SYS_NAND_ONFI_DETECTION
355
356
357#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
358 FTIM0_NAND_TWP(0x18) | \
359 FTIM0_NAND_TWCHT(0x07) | \
360 FTIM0_NAND_TWH(0x0a))
361#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
362 FTIM1_NAND_TWBE(0x39) | \
363 FTIM1_NAND_TRR(0x0e) | \
364 FTIM1_NAND_TRP(0x18))
365#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
366 FTIM2_NAND_TREH(0x0a) | \
367 FTIM2_NAND_TWHRE(0x1e))
368#define CONFIG_SYS_NAND_FTIM3 0x0
369
370#define CONFIG_SYS_NAND_DDR_LAW 11
371#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
372#define CONFIG_SYS_MAX_NAND_DEVICE 1
373#define CONFIG_CMD_NAND
374
375#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
376
377#if defined(CONFIG_NAND)
378#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
379#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
380#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
381#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
382#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
383#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
384#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
385#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
386#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
387#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
388#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
389#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
390#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
391#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
392#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
393#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
394#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
395#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
396#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
397#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
398#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
399#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
400#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
401#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
402#else
403#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
404#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
405#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
406#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
407#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
408#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
409#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
410#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
411#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
412#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
413#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
414#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
415#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
416#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
417#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
418#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
419#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
420#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
421#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
422#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
423#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
424#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
425#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
426#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
427#endif
428
429#ifdef CONFIG_SPL_BUILD
430#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
431#else
432#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
433#endif
434
435#if defined(CONFIG_RAMBOOT_PBL)
436#define CONFIG_SYS_RAMBOOT
437#endif
438
439#define CONFIG_BOARD_EARLY_INIT_R
440#define CONFIG_MISC_INIT_R
441
442#define CONFIG_HWCONFIG
443
444
445#define CONFIG_L1_INIT_RAM
446#define CONFIG_SYS_INIT_RAM_LOCK
447#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000
448#ifdef CONFIG_PHYS_64BIT
449#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
450#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
451
452#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
453 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
454 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
455#else
456#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000
457#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
458#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
459#endif
460#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
461
462#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
463 GENERATED_GBL_DATA_SIZE)
464#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
465
466#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
467#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
468
469
470#define CONFIG_CONS_INDEX 1
471#define CONFIG_SYS_NS16550_SERIAL
472#define CONFIG_SYS_NS16550_REG_SIZE 1
473#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
474
475#define CONFIG_SYS_BAUDRATE_TABLE \
476 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
477
478#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
479#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
480#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
481#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
482
483
484#ifdef CONFIG_ARCH_T1024
485#define CONFIG_FSL_DIU_FB
486#ifdef CONFIG_FSL_DIU_FB
487#define CONFIG_FSL_DIU_CH7301
488#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
489#define CONFIG_CMD_BMP
490#define CONFIG_VIDEO_LOGO
491#define CONFIG_VIDEO_BMP_LOGO
492#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
493
494
495
496
497#undef CONFIG_SYS_FLASH_EMPTY_INFO
498#endif
499#endif
500
501
502#define CONFIG_SYS_I2C
503#define CONFIG_SYS_I2C_FSL
504#define CONFIG_SYS_FSL_I2C_SPEED 50000
505#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
506#define CONFIG_SYS_FSL_I2C2_SPEED 50000
507#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
508#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
509#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
510
511#define I2C_MUX_PCA_ADDR 0x77
512#define I2C_MUX_PCA_ADDR_PRI 0x77
513#define I2C_MUX_PCA_ADDR_SEC 0x76
514#define I2C_RETIMER_ADDR 0x18
515
516
517#define I2C_MUX_CH_DEFAULT 0x8
518#define I2C_MUX_CH_DIU 0xC
519#define I2C_MUX_CH5 0xD
520#define I2C_MUX_CH7 0xF
521
522
523#define CONFIG_SYS_I2C_LDI_ADDR 0x38
524#define CONFIG_SYS_I2C_DVI_ADDR 0x75
525
526
527
528
529#define RTC
530#define CONFIG_RTC_DS3231 1
531#define CONFIG_SYS_I2C_RTC_ADDR 0x68
532
533
534
535
536#ifndef CONFIG_SPL_BUILD
537#endif
538#define CONFIG_SPI_FLASH_BAR
539#define CONFIG_SF_DEFAULT_SPEED 10000000
540#define CONFIG_SF_DEFAULT_MODE 0
541
542
543
544
545
546#define CONFIG_PCIE1
547#define CONFIG_PCIE2
548#define CONFIG_PCIE3
549#define CONFIG_FSL_PCI_INIT
550#define CONFIG_SYS_PCI_64BIT
551#define CONFIG_PCI_INDIRECT_BRIDGE
552
553#ifdef CONFIG_PCI
554
555#ifdef CONFIG_PCIE1
556#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
557#ifdef CONFIG_PHYS_64BIT
558#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
559#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
560#else
561#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
562#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
563#endif
564#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
565#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
566#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
567#ifdef CONFIG_PHYS_64BIT
568#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
569#else
570#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
571#endif
572#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
573#endif
574
575
576#ifdef CONFIG_PCIE2
577#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
578#ifdef CONFIG_PHYS_64BIT
579#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
580#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
581#else
582#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
583#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000
584#endif
585#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
586#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
587#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
588#ifdef CONFIG_PHYS_64BIT
589#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
590#else
591#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
592#endif
593#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
594#endif
595
596
597#ifdef CONFIG_PCIE3
598#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
599#ifdef CONFIG_PHYS_64BIT
600#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
601#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
602#else
603#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
604#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
605#endif
606#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000
607#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
608#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
609#ifdef CONFIG_PHYS_64BIT
610#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
611#else
612#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
613#endif
614#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
615#endif
616
617#define CONFIG_PCI_SCAN_SHOW
618#endif
619
620
621
622
623#define CONFIG_FSL_SATA_V2
624#ifdef CONFIG_FSL_SATA_V2
625#define CONFIG_LIBATA
626#define CONFIG_FSL_SATA
627#define CONFIG_SYS_SATA_MAX_DEVICE 1
628#define CONFIG_SATA1
629#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
630#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
631#define CONFIG_LBA48
632#define CONFIG_CMD_SATA
633#endif
634
635
636
637
638#define CONFIG_HAS_FSL_DR_USB
639
640#ifdef CONFIG_HAS_FSL_DR_USB
641#define CONFIG_USB_EHCI
642#define CONFIG_USB_EHCI_FSL
643#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
644#endif
645
646
647
648
649#ifdef CONFIG_MMC
650#define CONFIG_FSL_ESDHC
651#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
652#endif
653
654
655#ifndef CONFIG_NOBQFMAN
656#define CONFIG_SYS_DPAA_QBMAN
657#define CONFIG_SYS_BMAN_NUM_PORTALS 10
658#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
659#ifdef CONFIG_PHYS_64BIT
660#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
661#else
662#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
663#endif
664#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
665#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
666#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
667#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
668#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
669#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
670 CONFIG_SYS_BMAN_CENA_SIZE)
671#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
672#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
673#define CONFIG_SYS_QMAN_NUM_PORTALS 10
674#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
675#ifdef CONFIG_PHYS_64BIT
676#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
677#else
678#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
679#endif
680#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
681#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
682#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
683#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
684#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
685#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
686 CONFIG_SYS_QMAN_CENA_SIZE)
687#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
688#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
689
690#define CONFIG_SYS_DPAA_FMAN
691
692#define CONFIG_QE
693#define CONFIG_U_QE
694
695#if defined(CONFIG_SPIFLASH)
696
697
698
699
700#define CONFIG_SYS_QE_FW_IN_SPIFLASH
701#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
702#define CONFIG_SYS_QE_FW_ADDR 0x130000
703#elif defined(CONFIG_SDCARD)
704
705
706
707
708
709#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
710#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
711#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
712#elif defined(CONFIG_NAND)
713#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
714#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
715#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
716#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
717
718
719
720
721
722
723
724#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
725#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
726#else
727#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
728#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
729#define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
730#endif
731#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
732#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
733#endif
734
735#ifdef CONFIG_SYS_DPAA_FMAN
736#define CONFIG_FMAN_ENET
737#define CONFIG_PHYLIB_10G
738#define CONFIG_PHY_VITESSE
739#define CONFIG_PHY_REALTEK
740#define CONFIG_PHY_TERANETICS
741#define RGMII_PHY1_ADDR 0x1
742#define RGMII_PHY2_ADDR 0x2
743#define SGMII_CARD_AQ_PHY_ADDR_S3 0x3
744#define SGMII_CARD_AQ_PHY_ADDR_S4 0x4
745#define SGMII_CARD_AQ_PHY_ADDR_S5 0x5
746#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
747#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
748#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
749#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
750#endif
751
752#ifdef CONFIG_FMAN_ENET
753#define CONFIG_MII
754#define CONFIG_ETHPRIME "FM1@DTSEC4"
755#define CONFIG_PHY_GIGE
756#endif
757
758
759
760
761#ifdef CONFIG_MTD_NOR_FLASH
762#define CONFIG_MTD_DEVICE
763#define CONFIG_MTD_PARTITIONS
764#define CONFIG_CMD_MTDPARTS
765#define CONFIG_FLASH_CFI_MTD
766#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
767 "spi0=spife110000.0"
768#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
769 "128k(dtb),96m(fs),-(user);"\
770 "fff800000.flash:2m(uboot),9m(kernel),"\
771 "128k(dtb),96m(fs),-(user);spife110000.0:" \
772 "2m(uboot),9m(kernel),128k(dtb),-(user)"
773#endif
774
775
776
777
778#define CONFIG_LOADS_ECHO
779#define CONFIG_SYS_LOADS_BAUD_CHANGE
780
781
782
783
784#define CONFIG_CMD_DATE
785#define CONFIG_CMD_EEPROM
786#define CONFIG_CMD_ERRATA
787#define CONFIG_CMD_IRQ
788#define CONFIG_CMD_REGINFO
789
790#ifdef CONFIG_PCI
791#define CONFIG_CMD_PCI
792#endif
793
794
795
796
797#define CONFIG_SYS_LONGHELP
798#define CONFIG_CMDLINE_EDITING
799#define CONFIG_AUTO_COMPLETE
800#define CONFIG_SYS_LOAD_ADDR 0x2000000
801#ifdef CONFIG_CMD_KGDB
802#define CONFIG_SYS_CBSIZE 1024
803#else
804#define CONFIG_SYS_CBSIZE 256
805#endif
806#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
807#define CONFIG_SYS_MAXARGS 16
808#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
809
810
811
812
813
814
815#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
816#define CONFIG_SYS_BOOTM_LEN (64 << 20)
817
818#ifdef CONFIG_CMD_KGDB
819#define CONFIG_KGDB_BAUDRATE 230400
820#endif
821
822
823
824
825#define CONFIG_ROOTPATH "/opt/nfsroot"
826#define CONFIG_BOOTFILE "uImage"
827#define CONFIG_UBOOTPATH "u-boot.bin"
828#define CONFIG_LOADADDR 1000000
829#define CONFIG_BAUDRATE 115200
830#define __USB_PHY_TYPE utmi
831
832#define CONFIG_EXTRA_ENV_SETTINGS \
833 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \
834 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
835 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
836 "ramdiskfile=t1024qds/ramdisk.uboot\0" \
837 "fdtfile=t1024qds/t1024qds.dtb\0" \
838 "netdev=eth0\0" \
839 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
840 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
841 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
842 "tftpflash=tftpboot $loadaddr $uboot && " \
843 "protect off $ubootaddr +$filesize && " \
844 "erase $ubootaddr +$filesize && " \
845 "cp.b $loadaddr $ubootaddr $filesize && " \
846 "protect on $ubootaddr +$filesize && " \
847 "cmp.b $loadaddr $ubootaddr $filesize\0" \
848 "consoledev=ttyS0\0" \
849 "ramdiskaddr=2000000\0" \
850 "fdtaddr=d00000\0" \
851 "bdev=sda3\0"
852
853#define CONFIG_LINUX \
854 "setenv bootargs root=/dev/ram rw " \
855 "console=$consoledev,$baudrate $othbootargs;" \
856 "setenv ramdiskaddr 0x02000000;" \
857 "setenv fdtaddr 0x00c00000;" \
858 "setenv loadaddr 0x1000000;" \
859 "bootm $loadaddr $ramdiskaddr $fdtaddr"
860
861#define CONFIG_NFSBOOTCOMMAND \
862 "setenv bootargs root=/dev/nfs rw " \
863 "nfsroot=$serverip:$rootpath " \
864 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
865 "console=$consoledev,$baudrate $othbootargs;" \
866 "tftp $loadaddr $bootfile;" \
867 "tftp $fdtaddr $fdtfile;" \
868 "bootm $loadaddr - $fdtaddr"
869
870#define CONFIG_BOOTCOMMAND CONFIG_LINUX
871
872
873#ifdef CONFIG_FSL_CAAM
874#define CONFIG_CMD_HASH
875#define CONFIG_SHA_HW_ACCEL
876#endif
877
878#include <asm/fsl_secure_boot.h>
879
880#endif
881