1
2
3
4
5
6
7
8
9
10
11#ifndef __T1024RDB_H
12#define __T1024RDB_H
13
14
15#define CONFIG_SYS_BOOK3E_HV
16#define CONFIG_MP
17#define CONFIG_ENABLE_36BIT_PHYS
18
19#ifdef CONFIG_PHYS_64BIT
20#define CONFIG_ADDR_MAP 1
21#define CONFIG_SYS_NUM_ADDR_MAP 64
22#endif
23
24#define CONFIG_SYS_FSL_CPC
25#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
26
27#define CONFIG_ENV_OVERWRITE
28
29
30#ifdef CONFIG_ARCH_T1024
31#define CONFIG_DEEP_SLEEP
32#endif
33
34#ifdef CONFIG_RAMBOOT_PBL
35#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
36#define CONFIG_SPL_FLUSH_IMAGE
37#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
38#define CONFIG_SYS_TEXT_BASE 0x30001000
39#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
40#define CONFIG_SPL_PAD_TO 0x40000
41#define CONFIG_SPL_MAX_SIZE 0x28000
42#define RESET_VECTOR_OFFSET 0x27FFC
43#define BOOT_PAGE_OFFSET 0x27000
44#ifdef CONFIG_SPL_BUILD
45#define CONFIG_SPL_SKIP_RELOCATE
46#define CONFIG_SPL_COMMON_INIT_DDR
47#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
48#endif
49
50#ifdef CONFIG_NAND
51#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
52#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
53#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
54#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
55#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
56#if defined(CONFIG_TARGET_T1024RDB)
57#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg
58#elif defined(CONFIG_TARGET_T1023RDB)
59#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg
60#endif
61#define CONFIG_SPL_NAND_BOOT
62#endif
63
64#ifdef CONFIG_SPIFLASH
65#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
66#define CONFIG_SPL_SPI_FLASH_MINIMAL
67#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
68#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
69#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
70#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
71#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
72#ifndef CONFIG_SPL_BUILD
73#define CONFIG_SYS_MPC85XX_NO_RESETVEC
74#endif
75#if defined(CONFIG_TARGET_T1024RDB)
76#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg
77#elif defined(CONFIG_TARGET_T1023RDB)
78#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg
79#endif
80#define CONFIG_SPL_SPI_BOOT
81#endif
82
83#ifdef CONFIG_SDCARD
84#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
85#define CONFIG_SPL_MMC_MINIMAL
86#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
87#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
88#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
89#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
90#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
91#ifndef CONFIG_SPL_BUILD
92#define CONFIG_SYS_MPC85XX_NO_RESETVEC
93#endif
94#if defined(CONFIG_TARGET_T1024RDB)
95#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg
96#elif defined(CONFIG_TARGET_T1023RDB)
97#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg
98#endif
99#define CONFIG_SPL_MMC_BOOT
100#endif
101
102#endif
103
104#ifndef CONFIG_SYS_TEXT_BASE
105#define CONFIG_SYS_TEXT_BASE 0xeff40000
106#endif
107
108#ifndef CONFIG_RESET_VECTOR_ADDRESS
109#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
110#endif
111
112#ifdef CONFIG_MTD_NOR_FLASH
113#define CONFIG_FLASH_CFI_DRIVER
114#define CONFIG_SYS_FLASH_CFI
115#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
116#endif
117
118
119#define CONFIG_SRIO_PCIE_BOOT_MASTER
120
121
122
123
124#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
125#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000
126#ifdef CONFIG_PHYS_64BIT
127#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
128#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
129#else
130#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
131#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
132#endif
133
134
135
136
137#ifdef CONFIG_PHYS_64BIT
138#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
139#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
140#else
141#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
142#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
143#endif
144#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000
145
146#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
147#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001
148
149
150#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
151#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
152#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
153 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
154
155#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
156#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
157 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
158#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
159#endif
160
161#if defined(CONFIG_SPIFLASH)
162#define CONFIG_SYS_EXTRA_ENV_RELOC
163#define CONFIG_ENV_IS_IN_SPI_FLASH
164#define CONFIG_ENV_SPI_BUS 0
165#define CONFIG_ENV_SPI_CS 0
166#define CONFIG_ENV_SPI_MAX_HZ 10000000
167#define CONFIG_ENV_SPI_MODE 0
168#define CONFIG_ENV_SIZE 0x2000
169#define CONFIG_ENV_OFFSET 0x100000
170#if defined(CONFIG_TARGET_T1024RDB)
171#define CONFIG_ENV_SECT_SIZE 0x10000
172#elif defined(CONFIG_TARGET_T1023RDB)
173#define CONFIG_ENV_SECT_SIZE 0x40000
174#endif
175#elif defined(CONFIG_SDCARD)
176#define CONFIG_SYS_EXTRA_ENV_RELOC
177#define CONFIG_ENV_IS_IN_MMC
178#define CONFIG_SYS_MMC_ENV_DEV 0
179#define CONFIG_ENV_SIZE 0x2000
180#define CONFIG_ENV_OFFSET (512 * 0x800)
181#elif defined(CONFIG_NAND)
182#define CONFIG_SYS_EXTRA_ENV_RELOC
183#define CONFIG_ENV_IS_IN_NAND
184#define CONFIG_ENV_SIZE 0x2000
185#if defined(CONFIG_TARGET_T1024RDB)
186#define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
187#elif defined(CONFIG_TARGET_T1023RDB)
188#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
189#endif
190#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
191#define CONFIG_ENV_IS_IN_REMOTE
192#define CONFIG_ENV_ADDR 0xffe20000
193#define CONFIG_ENV_SIZE 0x2000
194#elif defined(CONFIG_ENV_IS_NOWHERE)
195#define CONFIG_ENV_SIZE 0x2000
196#else
197#define CONFIG_ENV_IS_IN_FLASH
198#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
199#define CONFIG_ENV_SIZE 0x2000
200#define CONFIG_ENV_SECT_SIZE 0x20000
201#endif
202
203#ifndef __ASSEMBLY__
204unsigned long get_board_sys_clk(void);
205unsigned long get_board_ddr_clk(void);
206#endif
207
208#define CONFIG_SYS_CLK_FREQ 100000000
209#define CONFIG_DDR_CLK_FREQ 100000000
210
211
212
213
214#define CONFIG_SYS_CACHE_STASHING
215#define CONFIG_BACKSIDE_L2_CACHE
216#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
217#define CONFIG_BTB
218#define CONFIG_DDR_ECC
219#ifdef CONFIG_DDR_ECC
220#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
221#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
222#endif
223
224#define CONFIG_SYS_MEMTEST_START 0x00200000
225#define CONFIG_SYS_MEMTEST_END 0x00400000
226#define CONFIG_SYS_ALT_MEMTEST
227#define CONFIG_PANIC_HANG
228
229
230
231
232#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
233#define CONFIG_SYS_L3_SIZE (256 << 10)
234#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
235#ifdef CONFIG_RAMBOOT_PBL
236#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
237#endif
238#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
239#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
240#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
241#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
242
243#ifdef CONFIG_PHYS_64BIT
244#define CONFIG_SYS_DCSRBAR 0xf0000000
245#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
246#endif
247
248
249#define CONFIG_ID_EEPROM
250#define CONFIG_SYS_I2C_EEPROM_NXID
251#define CONFIG_SYS_EEPROM_BUS_NUM 0
252#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
253#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
254#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
255#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
256
257
258
259
260#define CONFIG_VERY_BIG_RAM
261#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
262#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
263#define CONFIG_DIMM_SLOTS_PER_CTLR 1
264#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
265#define CONFIG_FSL_DDR_INTERACTIVE
266#if defined(CONFIG_TARGET_T1024RDB)
267#define CONFIG_DDR_SPD
268#define CONFIG_SYS_SPD_BUS_NUM 0
269#define SPD_EEPROM_ADDRESS 0x51
270#define CONFIG_SYS_SDRAM_SIZE 4096
271#elif defined(CONFIG_TARGET_T1023RDB)
272#define CONFIG_SYS_DDR_RAW_TIMING
273#define CONFIG_SYS_SDRAM_SIZE 2048
274#endif
275
276
277
278
279#define CONFIG_SYS_FLASH_BASE 0xe8000000
280#ifdef CONFIG_PHYS_64BIT
281#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
282#else
283#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
284#endif
285
286#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
287#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
288 CSPR_PORT_SIZE_16 | \
289 CSPR_MSEL_NOR | \
290 CSPR_V)
291#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
292
293
294#if defined(CONFIG_TARGET_T1024RDB)
295#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
296#elif defined(CONFIG_TARGET_T1023RDB)
297#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \
298 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
299#endif
300#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
301 FTIM0_NOR_TEADC(0x5) | \
302 FTIM0_NOR_TEAHC(0x5))
303#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
304 FTIM1_NOR_TRAD_NOR(0x1A) |\
305 FTIM1_NOR_TSEQRAD_NOR(0x13))
306#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
307 FTIM2_NOR_TCH(0x4) | \
308 FTIM2_NOR_TWPH(0x0E) | \
309 FTIM2_NOR_TWP(0x1c))
310#define CONFIG_SYS_NOR_FTIM3 0x0
311
312#define CONFIG_SYS_FLASH_QUIET_TEST
313#define CONFIG_FLASH_SHOW_PROGRESS 45
314
315#define CONFIG_SYS_MAX_FLASH_BANKS 1
316#define CONFIG_SYS_MAX_FLASH_SECT 1024
317#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
318#define CONFIG_SYS_FLASH_WRITE_TOUT 500
319
320#define CONFIG_SYS_FLASH_EMPTY_INFO
321#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
322
323#ifdef CONFIG_TARGET_T1024RDB
324
325#define CONFIG_SYS_CPLD_BASE 0xffdf0000
326#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
327#define CONFIG_SYS_CSPR2_EXT (0xf)
328#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
329 | CSPR_PORT_SIZE_8 \
330 | CSPR_MSEL_GPCM \
331 | CSPR_V)
332#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
333#define CONFIG_SYS_CSOR2 0x0
334
335
336#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
337 FTIM0_GPCM_TEADC(0x0e) | \
338 FTIM0_GPCM_TEAHC(0x0e))
339#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
340 FTIM1_GPCM_TRAD(0x1f))
341#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
342 FTIM2_GPCM_TCH(0x8) | \
343 FTIM2_GPCM_TWP(0x1f))
344#define CONFIG_SYS_CS2_FTIM3 0x0
345#endif
346
347
348#define CONFIG_NAND_FSL_IFC
349#define CONFIG_SYS_NAND_BASE 0xff800000
350#ifdef CONFIG_PHYS_64BIT
351#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
352#else
353#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
354#endif
355#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
356#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
357 | CSPR_PORT_SIZE_8 \
358 | CSPR_MSEL_NAND \
359 | CSPR_V)
360#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
361
362#if defined(CONFIG_TARGET_T1024RDB)
363#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
364 | CSOR_NAND_ECC_DEC_EN \
365 | CSOR_NAND_ECC_MODE_4 \
366 | CSOR_NAND_RAL_3 \
367 | CSOR_NAND_PGS_4K \
368 | CSOR_NAND_SPRZ_224 \
369 | CSOR_NAND_PB(64))
370#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
371#elif defined(CONFIG_TARGET_T1023RDB)
372#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
373 | CSOR_NAND_ECC_DEC_EN \
374 | CSOR_NAND_ECC_MODE_4 \
375 | CSOR_NAND_RAL_3 \
376 | CSOR_NAND_PGS_2K \
377 | CSOR_NAND_SPRZ_128 \
378 | CSOR_NAND_PB(64))
379#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
380#endif
381
382#define CONFIG_SYS_NAND_ONFI_DETECTION
383
384#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
385 FTIM0_NAND_TWP(0x18) | \
386 FTIM0_NAND_TWCHT(0x07) | \
387 FTIM0_NAND_TWH(0x0a))
388#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
389 FTIM1_NAND_TWBE(0x39) | \
390 FTIM1_NAND_TRR(0x0e) | \
391 FTIM1_NAND_TRP(0x18))
392#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
393 FTIM2_NAND_TREH(0x0a) | \
394 FTIM2_NAND_TWHRE(0x1e))
395#define CONFIG_SYS_NAND_FTIM3 0x0
396
397#define CONFIG_SYS_NAND_DDR_LAW 11
398#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
399#define CONFIG_SYS_MAX_NAND_DEVICE 1
400#define CONFIG_CMD_NAND
401
402#if defined(CONFIG_NAND)
403#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
404#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
405#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
406#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
407#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
408#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
409#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
410#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
411#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
412#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
413#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
414#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
415#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
416#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
417#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
418#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
419#else
420#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
421#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
422#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
423#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
424#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
425#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
426#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
427#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
428#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
429#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
430#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
431#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
432#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
433#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
434#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
435#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
436#endif
437
438#ifdef CONFIG_SPL_BUILD
439#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
440#else
441#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
442#endif
443
444#if defined(CONFIG_RAMBOOT_PBL)
445#define CONFIG_SYS_RAMBOOT
446#endif
447
448#define CONFIG_BOARD_EARLY_INIT_R
449#define CONFIG_MISC_INIT_R
450
451#define CONFIG_HWCONFIG
452
453
454#define CONFIG_L1_INIT_RAM
455#define CONFIG_SYS_INIT_RAM_LOCK
456#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000
457#ifdef CONFIG_PHYS_64BIT
458#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
459#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
460
461#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
462 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
463 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
464#else
465#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000
466#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
467#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
468#endif
469#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
470
471#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
472 GENERATED_GBL_DATA_SIZE)
473#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
474
475#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
476#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
477
478
479#define CONFIG_CONS_INDEX 1
480#define CONFIG_SYS_NS16550_SERIAL
481#define CONFIG_SYS_NS16550_REG_SIZE 1
482#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
483
484#define CONFIG_SYS_BAUDRATE_TABLE \
485 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
486
487#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
488#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
489#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
490#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
491
492
493#undef CONFIG_FSL_DIU_FB
494#ifdef CONFIG_FSL_DIU_FB
495#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
496#define CONFIG_CMD_BMP
497#define CONFIG_VIDEO_LOGO
498#define CONFIG_VIDEO_BMP_LOGO
499#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
500
501
502
503
504#undef CONFIG_SYS_FLASH_EMPTY_INFO
505#endif
506
507
508#define CONFIG_SYS_I2C
509#define CONFIG_SYS_I2C_FSL
510#define CONFIG_SYS_FSL_I2C_SPEED 50000
511#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
512#define CONFIG_SYS_FSL_I2C2_SPEED 50000
513#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
514#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
515#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
516
517#define I2C_PCA6408_BUS_NUM 1
518#define I2C_PCA6408_ADDR 0x20
519
520
521#define I2C_MUX_CH_DEFAULT 0x8
522
523
524
525
526#define RTC
527#define CONFIG_RTC_DS1337 1
528#define CONFIG_SYS_I2C_RTC_ADDR 0x68
529
530
531
532
533#define CONFIG_SPI_FLASH_BAR
534#define CONFIG_SF_DEFAULT_SPEED 10000000
535#define CONFIG_SF_DEFAULT_MODE 0
536
537
538
539
540
541#define CONFIG_PCIE1
542#define CONFIG_PCIE2
543#define CONFIG_PCIE3
544#ifdef CONFIG_ARCH_T1040
545#define CONFIG_PCIE4
546#endif
547#define CONFIG_FSL_PCI_INIT
548#define CONFIG_SYS_PCI_64BIT
549#define CONFIG_PCI_INDIRECT_BRIDGE
550
551#ifdef CONFIG_PCI
552
553#ifdef CONFIG_PCIE1
554#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
555#ifdef CONFIG_PHYS_64BIT
556#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
557#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
558#else
559#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
560#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
561#endif
562#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
563#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
564#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
565#ifdef CONFIG_PHYS_64BIT
566#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
567#else
568#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
569#endif
570#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
571#endif
572
573
574#ifdef CONFIG_PCIE2
575#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
576#ifdef CONFIG_PHYS_64BIT
577#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
578#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
579#else
580#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
581#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000
582#endif
583#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
584#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
585#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
586#ifdef CONFIG_PHYS_64BIT
587#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
588#else
589#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
590#endif
591#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
592#endif
593
594
595#ifdef CONFIG_PCIE3
596#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
597#ifdef CONFIG_PHYS_64BIT
598#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
599#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
600#else
601#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
602#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
603#endif
604#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000
605#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
606#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
607#ifdef CONFIG_PHYS_64BIT
608#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
609#else
610#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
611#endif
612#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
613#endif
614
615
616#ifdef CONFIG_PCIE4
617#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
618#ifdef CONFIG_PHYS_64BIT
619#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
620#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
621#else
622#define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000
623#define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000
624#endif
625#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000
626#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
627#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
628#ifdef CONFIG_PHYS_64BIT
629#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
630#else
631#define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000
632#endif
633#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000
634#endif
635
636#define CONFIG_PCI_SCAN_SHOW
637#endif
638
639
640
641
642#define CONFIG_HAS_FSL_DR_USB
643
644#ifdef CONFIG_HAS_FSL_DR_USB
645#define CONFIG_USB_EHCI
646#define CONFIG_USB_EHCI_FSL
647#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
648#endif
649
650
651
652
653#ifdef CONFIG_MMC
654#define CONFIG_FSL_ESDHC
655#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
656#endif
657
658
659#ifndef CONFIG_NOBQFMAN
660#define CONFIG_SYS_DPAA_QBMAN
661#define CONFIG_SYS_BMAN_NUM_PORTALS 10
662#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
663#ifdef CONFIG_PHYS_64BIT
664#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
665#else
666#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
667#endif
668#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
669#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
670#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
671#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
672#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
673#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
674 CONFIG_SYS_BMAN_CENA_SIZE)
675#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
676#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
677#define CONFIG_SYS_QMAN_NUM_PORTALS 10
678#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
679#ifdef CONFIG_PHYS_64BIT
680#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
681#else
682#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
683#endif
684#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
685#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
686#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
687#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
688#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
689#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
690 CONFIG_SYS_QMAN_CENA_SIZE)
691#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
692#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
693
694#define CONFIG_SYS_DPAA_FMAN
695
696#ifdef CONFIG_TARGET_T1024RDB
697#define CONFIG_QE
698#define CONFIG_U_QE
699#endif
700
701#if defined(CONFIG_SPIFLASH)
702
703
704
705
706#define CONFIG_SYS_QE_FW_IN_SPIFLASH
707#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
708#define CONFIG_SYS_QE_FW_ADDR 0x130000
709#elif defined(CONFIG_SDCARD)
710
711
712
713
714
715#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
716#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
717#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
718#elif defined(CONFIG_NAND)
719#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
720#if defined(CONFIG_TARGET_T1024RDB)
721#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
722#define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
723#elif defined(CONFIG_TARGET_T1023RDB)
724#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
725#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
726#endif
727#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
728
729
730
731
732
733
734
735#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
736#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
737#else
738#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
739#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
740#define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
741#endif
742#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
743#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
744#endif
745
746#ifdef CONFIG_SYS_DPAA_FMAN
747#define CONFIG_FMAN_ENET
748#define CONFIG_PHYLIB_10G
749#define CONFIG_PHY_REALTEK
750#define CONFIG_PHY_AQUANTIA
751#if defined(CONFIG_TARGET_T1024RDB)
752#define RGMII_PHY1_ADDR 0x2
753#define RGMII_PHY2_ADDR 0x6
754#define SGMII_AQR_PHY_ADDR 0x2
755#define FM1_10GEC1_PHY_ADDR 0x1
756#elif defined(CONFIG_TARGET_T1023RDB)
757#define RGMII_PHY1_ADDR 0x1
758#define SGMII_RTK_PHY_ADDR 0x3
759#define SGMII_AQR_PHY_ADDR 0x2
760#endif
761#endif
762
763#ifdef CONFIG_FMAN_ENET
764#define CONFIG_MII
765#define CONFIG_ETHPRIME "FM1@DTSEC4"
766#define CONFIG_PHY_GIGE
767#endif
768
769
770
771
772#ifdef CONFIG_MTD_NOR_FLASH
773#define CONFIG_MTD_DEVICE
774#define CONFIG_MTD_PARTITIONS
775#define CONFIG_CMD_MTDPARTS
776#define CONFIG_FLASH_CFI_MTD
777#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
778 "spi0=spife110000.1"
779#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
780 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
781 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \
782 "1m(uboot),5m(kernel),128k(dtb),-(user)"
783#endif
784
785
786
787
788#define CONFIG_LOADS_ECHO
789#define CONFIG_SYS_LOADS_BAUD_CHANGE
790
791
792
793
794#define CONFIG_CMD_DATE
795#define CONFIG_CMD_EEPROM
796#define CONFIG_CMD_ERRATA
797#define CONFIG_CMD_IRQ
798#define CONFIG_CMD_REGINFO
799
800#ifdef CONFIG_PCI
801#define CONFIG_CMD_PCI
802#endif
803
804
805
806
807#define CONFIG_SYS_LONGHELP
808#define CONFIG_CMDLINE_EDITING
809#define CONFIG_AUTO_COMPLETE
810#define CONFIG_SYS_LOAD_ADDR 0x2000000
811#ifdef CONFIG_CMD_KGDB
812#define CONFIG_SYS_CBSIZE 1024
813#else
814#define CONFIG_SYS_CBSIZE 256
815#endif
816#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
817#define CONFIG_SYS_MAXARGS 16
818#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
819
820
821
822
823
824
825#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
826#define CONFIG_SYS_BOOTM_LEN (64 << 20)
827
828#ifdef CONFIG_CMD_KGDB
829#define CONFIG_KGDB_BAUDRATE 230400
830#endif
831
832
833
834
835#define CONFIG_ROOTPATH "/opt/nfsroot"
836#define CONFIG_BOOTFILE "uImage"
837#define CONFIG_UBOOTPATH u-boot.bin
838#define CONFIG_LOADADDR 1000000
839#define CONFIG_BAUDRATE 115200
840#define __USB_PHY_TYPE utmi
841
842#ifdef CONFIG_ARCH_T1024
843#define CONFIG_BOARDNAME t1024rdb
844#define BANK_INTLV cs0_cs1
845#else
846#define CONFIG_BOARDNAME t1023rdb
847#define BANK_INTLV null
848#endif
849
850#define CONFIG_EXTRA_ENV_SETTINGS \
851 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
852 "bank_intlv=" __stringify(BANK_INTLV) "\0" \
853 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
854 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
855 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \
856 __stringify(CONFIG_BOARDNAME) ".dtb\0" \
857 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
858 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
859 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
860 "netdev=eth0\0" \
861 "tftpflash=tftpboot $loadaddr $uboot && " \
862 "protect off $ubootaddr +$filesize && " \
863 "erase $ubootaddr +$filesize && " \
864 "cp.b $loadaddr $ubootaddr $filesize && " \
865 "protect on $ubootaddr +$filesize && " \
866 "cmp.b $loadaddr $ubootaddr $filesize\0" \
867 "consoledev=ttyS0\0" \
868 "ramdiskaddr=2000000\0" \
869 "fdtaddr=1e00000\0" \
870 "bdev=sda3\0"
871
872#define CONFIG_LINUX \
873 "setenv bootargs root=/dev/ram rw " \
874 "console=$consoledev,$baudrate $othbootargs;" \
875 "setenv ramdiskaddr 0x02000000;" \
876 "setenv fdtaddr 0x00c00000;" \
877 "setenv loadaddr 0x1000000;" \
878 "bootm $loadaddr $ramdiskaddr $fdtaddr"
879
880#define CONFIG_NFSBOOTCOMMAND \
881 "setenv bootargs root=/dev/nfs rw " \
882 "nfsroot=$serverip:$rootpath " \
883 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
884 "console=$consoledev,$baudrate $othbootargs;" \
885 "tftp $loadaddr $bootfile;" \
886 "tftp $fdtaddr $fdtfile;" \
887 "bootm $loadaddr - $fdtaddr"
888
889#define CONFIG_BOOTCOMMAND CONFIG_LINUX
890
891
892#ifdef CONFIG_FSL_CAAM
893#define CONFIG_CMD_HASH
894#define CONFIG_SHA_HW_ACCEL
895#endif
896
897#include <asm/fsl_secure_boot.h>
898
899#endif
900