1
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5
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
10
11
12
13#include <asm/config_mpc85xx.h>
14
15#ifdef CONFIG_RAMBOOT_PBL
16
17#ifndef CONFIG_SECURE_BOOT
18#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
19#else
20#define CONFIG_SYS_FSL_PBL_PBI \
21 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg
22#endif
23
24#define CONFIG_SPL_FLUSH_IMAGE
25#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
26#define CONFIG_SYS_TEXT_BASE 0x30001000
27#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
28#define CONFIG_SPL_PAD_TO 0x40000
29#define CONFIG_SPL_MAX_SIZE 0x28000
30#ifdef CONFIG_SPL_BUILD
31#define CONFIG_SPL_SKIP_RELOCATE
32#define CONFIG_SPL_COMMON_INIT_DDR
33#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
34#endif
35#define RESET_VECTOR_OFFSET 0x27FFC
36#define BOOT_PAGE_OFFSET 0x27000
37
38#ifdef CONFIG_NAND
39#ifdef CONFIG_SECURE_BOOT
40#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
41
42
43
44
45#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \
46 CONFIG_U_BOOT_HDR_SIZE)
47#else
48#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
49#endif
50#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
51#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
52#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
53#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
54#ifdef CONFIG_TARGET_T1040RDB
55#define CONFIG_SYS_FSL_PBL_RCW \
56$(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg
57#endif
58#ifdef CONFIG_TARGET_T1042RDB_PI
59#define CONFIG_SYS_FSL_PBL_RCW \
60$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg
61#endif
62#ifdef CONFIG_TARGET_T1042RDB
63#define CONFIG_SYS_FSL_PBL_RCW \
64$(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg
65#endif
66#ifdef CONFIG_TARGET_T1040D4RDB
67#define CONFIG_SYS_FSL_PBL_RCW \
68$(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg
69#endif
70#ifdef CONFIG_TARGET_T1042D4RDB
71#define CONFIG_SYS_FSL_PBL_RCW \
72$(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg
73#endif
74#define CONFIG_SPL_NAND_BOOT
75#endif
76
77#ifdef CONFIG_SPIFLASH
78#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
79#define CONFIG_SPL_SPI_FLASH_MINIMAL
80#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
81#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
82#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
83#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
84#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
85#ifndef CONFIG_SPL_BUILD
86#define CONFIG_SYS_MPC85XX_NO_RESETVEC
87#endif
88#ifdef CONFIG_TARGET_T1040RDB
89#define CONFIG_SYS_FSL_PBL_RCW \
90$(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg
91#endif
92#ifdef CONFIG_TARGET_T1042RDB_PI
93#define CONFIG_SYS_FSL_PBL_RCW \
94$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg
95#endif
96#ifdef CONFIG_TARGET_T1042RDB
97#define CONFIG_SYS_FSL_PBL_RCW \
98$(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg
99#endif
100#ifdef CONFIG_TARGET_T1040D4RDB
101#define CONFIG_SYS_FSL_PBL_RCW \
102$(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg
103#endif
104#ifdef CONFIG_TARGET_T1042D4RDB
105#define CONFIG_SYS_FSL_PBL_RCW \
106$(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg
107#endif
108#define CONFIG_SPL_SPI_BOOT
109#endif
110
111#ifdef CONFIG_SDCARD
112#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
113#define CONFIG_SPL_MMC_MINIMAL
114#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
115#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
116#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
117#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
118#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
119#ifndef CONFIG_SPL_BUILD
120#define CONFIG_SYS_MPC85XX_NO_RESETVEC
121#endif
122#ifdef CONFIG_TARGET_T1040RDB
123#define CONFIG_SYS_FSL_PBL_RCW \
124$(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg
125#endif
126#ifdef CONFIG_TARGET_T1042RDB_PI
127#define CONFIG_SYS_FSL_PBL_RCW \
128$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg
129#endif
130#ifdef CONFIG_TARGET_T1042RDB
131#define CONFIG_SYS_FSL_PBL_RCW \
132$(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg
133#endif
134#ifdef CONFIG_TARGET_T1040D4RDB
135#define CONFIG_SYS_FSL_PBL_RCW \
136$(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg
137#endif
138#ifdef CONFIG_TARGET_T1042D4RDB
139#define CONFIG_SYS_FSL_PBL_RCW \
140$(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
141#endif
142#define CONFIG_SPL_MMC_BOOT
143#endif
144
145#endif
146
147
148#define CONFIG_SYS_BOOK3E_HV
149#define CONFIG_MP
150
151
152#define CONFIG_DEEP_SLEEP
153
154#ifndef CONFIG_SYS_TEXT_BASE
155#define CONFIG_SYS_TEXT_BASE 0xeff40000
156#endif
157
158#ifndef CONFIG_RESET_VECTOR_ADDRESS
159#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
160#endif
161
162#define CONFIG_SYS_FSL_CPC
163#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
164#define CONFIG_PCI_INDIRECT_BRIDGE
165#define CONFIG_PCIE1
166#define CONFIG_PCIE2
167#define CONFIG_PCIE3
168#define CONFIG_PCIE4
169
170#define CONFIG_FSL_PCI_INIT
171#define CONFIG_SYS_PCI_64BIT
172
173#define CONFIG_ENV_OVERWRITE
174
175#ifdef CONFIG_MTD_NOR_FLASH
176#define CONFIG_FLASH_CFI_DRIVER
177#define CONFIG_SYS_FLASH_CFI
178#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
179#endif
180
181#if defined(CONFIG_SPIFLASH)
182#define CONFIG_SYS_EXTRA_ENV_RELOC
183#define CONFIG_ENV_IS_IN_SPI_FLASH
184#define CONFIG_ENV_SIZE 0x2000
185#define CONFIG_ENV_OFFSET 0x100000
186#define CONFIG_ENV_SECT_SIZE 0x10000
187#elif defined(CONFIG_SDCARD)
188#define CONFIG_SYS_EXTRA_ENV_RELOC
189#define CONFIG_ENV_IS_IN_MMC
190#define CONFIG_SYS_MMC_ENV_DEV 0
191#define CONFIG_ENV_SIZE 0x2000
192#define CONFIG_ENV_OFFSET (512 * 0x800)
193#elif defined(CONFIG_NAND)
194#ifdef CONFIG_SECURE_BOOT
195#define CONFIG_RAMBOOT_NAND
196#define CONFIG_BOOTSCRIPT_COPY_RAM
197#endif
198#define CONFIG_SYS_EXTRA_ENV_RELOC
199#define CONFIG_ENV_IS_IN_NAND
200#define CONFIG_ENV_SIZE 0x2000
201#define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
202#else
203#define CONFIG_ENV_IS_IN_FLASH
204#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
205#define CONFIG_ENV_SIZE 0x2000
206#define CONFIG_ENV_SECT_SIZE 0x20000
207#endif
208
209#define CONFIG_SYS_CLK_FREQ 100000000
210#define CONFIG_DDR_CLK_FREQ 66666666
211
212
213
214
215#define CONFIG_SYS_CACHE_STASHING
216#define CONFIG_BACKSIDE_L2_CACHE
217#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
218#define CONFIG_BTB
219#define CONFIG_DDR_ECC
220#ifdef CONFIG_DDR_ECC
221#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
222#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
223#endif
224
225#define CONFIG_ENABLE_36BIT_PHYS
226
227#define CONFIG_ADDR_MAP
228#define CONFIG_SYS_NUM_ADDR_MAP 64
229
230#define CONFIG_SYS_MEMTEST_START 0x00200000
231#define CONFIG_SYS_MEMTEST_END 0x00400000
232#define CONFIG_SYS_ALT_MEMTEST
233#define CONFIG_PANIC_HANG
234
235
236
237
238#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
239
240
241
242
243
244#define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000
245#define CONFIG_SYS_L3_SIZE 256 << 10
246#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
247#ifdef CONFIG_RAMBOOT_PBL
248#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
249#endif
250#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
251#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
252#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
253#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
254
255#define CONFIG_SYS_DCSRBAR 0xf0000000
256#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
257
258
259
260
261#define CONFIG_VERY_BIG_RAM
262#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
263#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
264
265#define CONFIG_DIMM_SLOTS_PER_CTLR 1
266#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
267
268#define CONFIG_DDR_SPD
269
270#define CONFIG_SYS_SPD_BUS_NUM 0
271#define SPD_EEPROM_ADDRESS 0x51
272
273#define CONFIG_SYS_SDRAM_SIZE 4096
274
275
276
277
278#define CONFIG_SYS_FLASH_BASE 0xe8000000
279#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
280
281#define CONFIG_SYS_NOR_CSPR_EXT (0xf)
282#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
283 CSPR_PORT_SIZE_16 | \
284 CSPR_MSEL_NOR | \
285 CSPR_V)
286#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
287
288
289
290
291#define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
292
293
294#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
295#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
296 FTIM0_NOR_TEADC(0x5) | \
297 FTIM0_NOR_TEAHC(0x5))
298#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
299 FTIM1_NOR_TRAD_NOR(0x1A) |\
300 FTIM1_NOR_TSEQRAD_NOR(0x13))
301#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
302 FTIM2_NOR_TCH(0x4) | \
303 FTIM2_NOR_TWPH(0x0E) | \
304 FTIM2_NOR_TWP(0x1c))
305#define CONFIG_SYS_NOR_FTIM3 0x0
306
307#define CONFIG_SYS_FLASH_QUIET_TEST
308#define CONFIG_FLASH_SHOW_PROGRESS 45
309
310#define CONFIG_SYS_MAX_FLASH_BANKS 2
311#define CONFIG_SYS_MAX_FLASH_SECT 1024
312#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
313#define CONFIG_SYS_FLASH_WRITE_TOUT 500
314
315#define CONFIG_SYS_FLASH_EMPTY_INFO
316#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
317
318
319#define CPLD_LBMAP_MASK 0x3F
320#define CPLD_BANK_SEL_MASK 0x07
321#define CPLD_BANK_OVERRIDE 0x40
322#define CPLD_LBMAP_ALTBANK 0x44
323#define CPLD_LBMAP_DFLTBANK 0x40
324#define CPLD_LBMAP_RESET 0xFF
325#define CPLD_LBMAP_SHIFT 0x03
326
327#if defined(CONFIG_TARGET_T1042RDB_PI)
328#define CPLD_DIU_SEL_DFP 0x80
329#elif defined(CONFIG_TARGET_T1042D4RDB)
330#define CPLD_DIU_SEL_DFP 0xc0
331#endif
332
333#if defined(CONFIG_TARGET_T1040D4RDB)
334#define CPLD_INT_MASK_ALL 0xFF
335#define CPLD_INT_MASK_THERM 0x80
336#define CPLD_INT_MASK_DVI_DFP 0x40
337#define CPLD_INT_MASK_QSGMII1 0x20
338#define CPLD_INT_MASK_QSGMII2 0x10
339#define CPLD_INT_MASK_SGMI1 0x08
340#define CPLD_INT_MASK_SGMI2 0x04
341#define CPLD_INT_MASK_TDMR1 0x02
342#define CPLD_INT_MASK_TDMR2 0x01
343#endif
344
345#define CONFIG_SYS_CPLD_BASE 0xffdf0000
346#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
347#define CONFIG_SYS_CSPR2_EXT (0xf)
348#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
349 | CSPR_PORT_SIZE_8 \
350 | CSPR_MSEL_GPCM \
351 | CSPR_V)
352#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
353#define CONFIG_SYS_CSOR2 0x0
354
355#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
356 FTIM0_GPCM_TEADC(0x0e) | \
357 FTIM0_GPCM_TEAHC(0x0e))
358#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
359 FTIM1_GPCM_TRAD(0x1f))
360#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
361 FTIM2_GPCM_TCH(0x8) | \
362 FTIM2_GPCM_TWP(0x1f))
363#define CONFIG_SYS_CS2_FTIM3 0x0
364
365
366#define CONFIG_NAND_FSL_IFC
367#define CONFIG_SYS_NAND_BASE 0xff800000
368#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
369
370#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
371#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
372 | CSPR_PORT_SIZE_8 \
373 | CSPR_MSEL_NAND \
374 | CSPR_V)
375#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
376
377#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
378 | CSOR_NAND_ECC_DEC_EN \
379 | CSOR_NAND_ECC_MODE_4 \
380 | CSOR_NAND_RAL_3 \
381 | CSOR_NAND_PGS_4K \
382 | CSOR_NAND_SPRZ_224 \
383 | CSOR_NAND_PB(64))
384
385#define CONFIG_SYS_NAND_ONFI_DETECTION
386
387
388#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
389 FTIM0_NAND_TWP(0x18) | \
390 FTIM0_NAND_TWCHT(0x07) | \
391 FTIM0_NAND_TWH(0x0a))
392#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
393 FTIM1_NAND_TWBE(0x39) | \
394 FTIM1_NAND_TRR(0x0e) | \
395 FTIM1_NAND_TRP(0x18))
396#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
397 FTIM2_NAND_TREH(0x0a) | \
398 FTIM2_NAND_TWHRE(0x1e))
399#define CONFIG_SYS_NAND_FTIM3 0x0
400
401#define CONFIG_SYS_NAND_DDR_LAW 11
402#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
403#define CONFIG_SYS_MAX_NAND_DEVICE 1
404#define CONFIG_CMD_NAND
405
406#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
407
408#if defined(CONFIG_NAND)
409#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
410#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
411#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
412#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
413#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
414#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
415#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
416#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
417#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
418#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
419#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
420#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
421#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
422#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
423#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
424#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
425#else
426#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
427#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
428#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
429#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
430#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
431#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
432#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
433#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
434#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
435#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
436#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
437#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
438#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
439#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
440#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
441#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
442#endif
443
444#ifdef CONFIG_SPL_BUILD
445#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
446#else
447#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
448#endif
449
450#if defined(CONFIG_RAMBOOT_PBL)
451#define CONFIG_SYS_RAMBOOT
452#endif
453
454#ifdef CONFIG_SYS_FSL_ERRATUM_A008044
455#if defined(CONFIG_NAND)
456#define CONFIG_A008044_WORKAROUND
457#endif
458#endif
459
460#define CONFIG_BOARD_EARLY_INIT_R
461#define CONFIG_MISC_INIT_R
462
463#define CONFIG_HWCONFIG
464
465
466#define CONFIG_L1_INIT_RAM
467#define CONFIG_SYS_INIT_RAM_LOCK
468#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000
469#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
470#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
471
472#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
473 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
474 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
475#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
476
477#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
478 GENERATED_GBL_DATA_SIZE)
479#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
480
481#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
482#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
483
484
485
486
487
488#define CONFIG_CONS_INDEX 1
489#define CONFIG_SYS_NS16550_SERIAL
490#define CONFIG_SYS_NS16550_REG_SIZE 1
491#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
492
493#define CONFIG_SYS_BAUDRATE_TABLE \
494 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
495
496#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
497#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
498#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
499#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
500
501#if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB)
502
503#define CONFIG_FSL_DIU_FB
504
505#ifdef CONFIG_FSL_DIU_FB
506#define CONFIG_FSL_DIU_CH7301
507#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
508#define CONFIG_CMD_BMP
509#define CONFIG_VIDEO_LOGO
510#define CONFIG_VIDEO_BMP_LOGO
511#endif
512#endif
513
514
515#define CONFIG_SYS_I2C
516#define CONFIG_SYS_I2C_FSL
517#define CONFIG_SYS_FSL_I2C_SPEED 400000
518#define CONFIG_SYS_FSL_I2C2_SPEED 400000
519#define CONFIG_SYS_FSL_I2C3_SPEED 400000
520#define CONFIG_SYS_FSL_I2C4_SPEED 400000
521#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
522#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
523#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
524#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
525#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
526#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
527#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
528#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
529
530
531#define I2C_MUX_PCA_ADDR 0x70
532#define I2C_MUX_CH_DEFAULT 0x8
533
534#if defined(CONFIG_TARGET_T1042RDB_PI) || \
535 defined(CONFIG_TARGET_T1040D4RDB) || \
536 defined(CONFIG_TARGET_T1042D4RDB)
537
538#define CONFIG_SYS_I2C_LDI_ADDR 0x38
539#define CONFIG_SYS_I2C_DVI_ADDR 0x75
540
541
542
543
544#define RTC
545#define CONFIG_RTC_DS1337 1
546#define CONFIG_SYS_I2C_RTC_ADDR 0x68
547
548
549#define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
550#endif
551
552
553
554
555#define CONFIG_SPI_FLASH_BAR
556#define CONFIG_SF_DEFAULT_SPEED 10000000
557#define CONFIG_SF_DEFAULT_MODE 0
558#define CONFIG_ENV_SPI_BUS 0
559#define CONFIG_ENV_SPI_CS 0
560#define CONFIG_ENV_SPI_MAX_HZ 10000000
561#define CONFIG_ENV_SPI_MODE 0
562
563
564
565
566
567
568#ifdef CONFIG_PCI
569
570#ifdef CONFIG_PCIE1
571#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
572#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
573#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
574#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
575#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
576#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
577#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
578#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
579#endif
580
581
582#ifdef CONFIG_PCIE2
583#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
584#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
585#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
586#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
587#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
588#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
589#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
590#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
591#endif
592
593
594#ifdef CONFIG_PCIE3
595#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
596#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
597#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
598#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000
599#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
600#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
601#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
602#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
603#endif
604
605
606#ifdef CONFIG_PCIE4
607#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
608#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
609#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
610#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000
611#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
612#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
613#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
614#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000
615#endif
616
617#define CONFIG_PCI_SCAN_SHOW
618#endif
619
620
621#define CONFIG_FSL_SATA_V2
622#ifdef CONFIG_FSL_SATA_V2
623#define CONFIG_LIBATA
624#define CONFIG_FSL_SATA
625
626#define CONFIG_SYS_SATA_MAX_DEVICE 1
627#define CONFIG_SATA1
628#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
629#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
630
631#define CONFIG_LBA48
632#define CONFIG_CMD_SATA
633#endif
634
635
636
637
638#define CONFIG_HAS_FSL_DR_USB
639
640#ifdef CONFIG_HAS_FSL_DR_USB
641#define CONFIG_USB_EHCI
642
643#ifdef CONFIG_USB_EHCI
644#define CONFIG_USB_EHCI_FSL
645#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
646#endif
647#endif
648
649#ifdef CONFIG_MMC
650#define CONFIG_FSL_ESDHC
651#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
652#endif
653
654
655#ifndef CONFIG_NOBQFMAN
656#define CONFIG_SYS_DPAA_QBMAN
657#define CONFIG_SYS_BMAN_NUM_PORTALS 10
658#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
659#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
660#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
661#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
662#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
663#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
664#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
665#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
666 CONFIG_SYS_BMAN_CENA_SIZE)
667#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
668#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
669#define CONFIG_SYS_QMAN_NUM_PORTALS 10
670#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
671#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
672#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
673#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
674#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
675#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
676#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
677#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
678 CONFIG_SYS_QMAN_CENA_SIZE)
679#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
680#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
681
682#define CONFIG_SYS_DPAA_FMAN
683#define CONFIG_SYS_DPAA_PME
684
685#define CONFIG_QE
686#define CONFIG_U_QE
687
688
689#if defined(CONFIG_SPIFLASH)
690
691
692
693
694#define CONFIG_SYS_QE_FW_IN_SPIFLASH
695#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
696#elif defined(CONFIG_SDCARD)
697
698
699
700
701
702#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
703#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
704#elif defined(CONFIG_NAND)
705#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
706#define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
707#else
708#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
709#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
710#endif
711
712#if defined(CONFIG_SPIFLASH)
713#define CONFIG_SYS_QE_FW_ADDR 0x130000
714#elif defined(CONFIG_SDCARD)
715#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
716#elif defined(CONFIG_NAND)
717#define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
718#else
719#define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
720#endif
721
722#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
723#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
724#endif
725
726#ifdef CONFIG_SYS_DPAA_FMAN
727#define CONFIG_FMAN_ENET
728#define CONFIG_PHY_VITESSE
729#define CONFIG_PHY_REALTEK
730#endif
731
732#ifdef CONFIG_FMAN_ENET
733#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
734#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
735#elif defined(CONFIG_TARGET_T1040D4RDB)
736#define CONFIG_SYS_SGMII1_PHY_ADDR 0x01
737#elif defined(CONFIG_TARGET_T1042D4RDB)
738#define CONFIG_SYS_SGMII1_PHY_ADDR 0x02
739#define CONFIG_SYS_SGMII2_PHY_ADDR 0x03
740#define CONFIG_SYS_SGMII3_PHY_ADDR 0x01
741#endif
742
743#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
744#define CONFIG_SYS_RGMII1_PHY_ADDR 0x04
745#define CONFIG_SYS_RGMII2_PHY_ADDR 0x05
746#else
747#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
748#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
749#endif
750
751
752#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
753#define CONFIG_VSC9953
754#define CONFIG_CMD_ETHSW
755#ifdef CONFIG_TARGET_T1040RDB
756#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
757#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
758#else
759#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08
760#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c
761#endif
762#endif
763
764#define CONFIG_MII
765#define CONFIG_ETHPRIME "FM1@DTSEC4"
766#define CONFIG_PHY_GIGE
767#endif
768
769
770
771
772#define CONFIG_LOADS_ECHO
773#define CONFIG_SYS_LOADS_BAUD_CHANGE
774
775
776
777
778#ifdef CONFIG_TARGET_T1042RDB_PI
779#define CONFIG_CMD_DATE
780#endif
781#define CONFIG_CMD_ERRATA
782#define CONFIG_CMD_IRQ
783#define CONFIG_CMD_REGINFO
784
785#ifdef CONFIG_PCI
786#define CONFIG_CMD_PCI
787#endif
788
789
790#ifdef CONFIG_FSL_CAAM
791#define CONFIG_CMD_HASH
792#define CONFIG_SHA_HW_ACCEL
793#endif
794
795
796
797
798#define CONFIG_SYS_LONGHELP
799#define CONFIG_CMDLINE_EDITING
800#define CONFIG_AUTO_COMPLETE
801#define CONFIG_SYS_LOAD_ADDR 0x2000000
802#ifdef CONFIG_CMD_KGDB
803#define CONFIG_SYS_CBSIZE 1024
804#else
805#define CONFIG_SYS_CBSIZE 256
806#endif
807#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
808#define CONFIG_SYS_MAXARGS 16
809#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
810
811
812
813
814
815
816#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
817#define CONFIG_SYS_BOOTM_LEN (64 << 20)
818
819#ifdef CONFIG_CMD_KGDB
820#define CONFIG_KGDB_BAUDRATE 230400
821#endif
822
823
824
825
826#ifdef CONFIG_MTD_NOR_FLASH
827#define CONFIG_MTD_DEVICE
828#define CONFIG_MTD_PARTITIONS
829#define CONFIG_CMD_MTDPARTS
830#define CONFIG_FLASH_CFI_MTD
831#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
832 "spi0=spife110000.0"
833#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
834 "128k(dtb),96m(fs),-(user);"\
835 "fff800000.flash:2m(uboot),9m(kernel),"\
836 "128k(dtb),96m(fs),-(user);spife110000.0:" \
837 "2m(uboot),9m(kernel),128k(dtb),-(user)"
838#endif
839
840
841
842
843#define CONFIG_ROOTPATH "/opt/nfsroot"
844#define CONFIG_BOOTFILE "uImage"
845#define CONFIG_UBOOTPATH "u-boot.bin"
846
847
848#define CONFIG_LOADADDR 1000000
849
850
851#define CONFIG_BAUDRATE 115200
852
853#define __USB_PHY_TYPE utmi
854#define RAMDISKFILE "t104xrdb/ramdisk.uboot"
855
856#ifdef CONFIG_TARGET_T1040RDB
857#define FDTFILE "t1040rdb/t1040rdb.dtb"
858#elif defined(CONFIG_TARGET_T1042RDB_PI)
859#define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb"
860#elif defined(CONFIG_TARGET_T1042RDB)
861#define FDTFILE "t1042rdb/t1042rdb.dtb"
862#elif defined(CONFIG_TARGET_T1040D4RDB)
863#define FDTFILE "t1042rdb/t1040d4rdb.dtb"
864#elif defined(CONFIG_TARGET_T1042D4RDB)
865#define FDTFILE "t1042rdb/t1042d4rdb.dtb"
866#endif
867
868#ifdef CONFIG_FSL_DIU_FB
869#define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
870#else
871#define DIU_ENVIRONMENT
872#endif
873
874#define CONFIG_EXTRA_ENV_SETTINGS \
875 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
876 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
877 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
878 "netdev=eth0\0" \
879 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \
880 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
881 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
882 "tftpflash=tftpboot $loadaddr $uboot && " \
883 "protect off $ubootaddr +$filesize && " \
884 "erase $ubootaddr +$filesize && " \
885 "cp.b $loadaddr $ubootaddr $filesize && " \
886 "protect on $ubootaddr +$filesize && " \
887 "cmp.b $loadaddr $ubootaddr $filesize\0" \
888 "consoledev=ttyS0\0" \
889 "ramdiskaddr=2000000\0" \
890 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
891 "fdtaddr=1e00000\0" \
892 "fdtfile=" __stringify(FDTFILE) "\0" \
893 "bdev=sda3\0"
894
895#define CONFIG_LINUX \
896 "setenv bootargs root=/dev/ram rw " \
897 "console=$consoledev,$baudrate $othbootargs;" \
898 "setenv ramdiskaddr 0x02000000;" \
899 "setenv fdtaddr 0x00c00000;" \
900 "setenv loadaddr 0x1000000;" \
901 "bootm $loadaddr $ramdiskaddr $fdtaddr"
902
903#define CONFIG_HDBOOT \
904 "setenv bootargs root=/dev/$bdev rw " \
905 "console=$consoledev,$baudrate $othbootargs;" \
906 "tftp $loadaddr $bootfile;" \
907 "tftp $fdtaddr $fdtfile;" \
908 "bootm $loadaddr - $fdtaddr"
909
910#define CONFIG_NFSBOOTCOMMAND \
911 "setenv bootargs root=/dev/nfs rw " \
912 "nfsroot=$serverip:$rootpath " \
913 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
914 "console=$consoledev,$baudrate $othbootargs;" \
915 "tftp $loadaddr $bootfile;" \
916 "tftp $fdtaddr $fdtfile;" \
917 "bootm $loadaddr - $fdtaddr"
918
919#define CONFIG_RAMBOOTCOMMAND \
920 "setenv bootargs root=/dev/ram rw " \
921 "console=$consoledev,$baudrate $othbootargs;" \
922 "tftp $ramdiskaddr $ramdiskfile;" \
923 "tftp $loadaddr $bootfile;" \
924 "tftp $fdtaddr $fdtfile;" \
925 "bootm $loadaddr $ramdiskaddr $fdtaddr"
926
927#define CONFIG_BOOTCOMMAND CONFIG_LINUX
928
929#include <asm/fsl_secure_boot.h>
930
931#endif
932