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12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15
16
17
18#define CONFIG_E300 1
19#define CONFIG_MPC834x 1
20#define CONFIG_MPC8349 1
21#define CONFIG_TQM834X 1
22
23#define CONFIG_SYS_TEXT_BASE 0x80000000
24
25
26#define CONFIG_SYS_IMMR 0xff400000
27
28
29#define CONFIG_83XX_CLKIN 66666000
30
31
32
33
34
35
36
37
38
39
40#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
41#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
42
43
44
45
46#define CONFIG_BOARD_EARLY_INIT_R
47
48
49
50
51
52#define CONFIG_SYS_DDR_BASE 0x00000000
53#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
54#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
55#define DDR_CASLAT_25
56#undef CONFIG_DDR_ECC
57#undef CONFIG_SPD_EEPROM
58
59#undef CONFIG_SYS_DRAM_TEST
60#define CONFIG_SYS_MEMTEST_START 0x00000000
61#define CONFIG_SYS_MEMTEST_END 0x00100000
62
63
64
65
66#define CONFIG_SYS_FLASH_CFI
67#define CONFIG_FLASH_CFI_DRIVER
68#undef CONFIG_SYS_FLASH_CHECKSUM
69#define CONFIG_SYS_FLASH_BASE 0x80000000
70#define CONFIG_SYS_FLASH_SIZE 8
71#define CONFIG_SYS_FLASH_EMPTY_INFO
72#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
73
74
75
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83
84
85
86
87
88#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
89
90#define CONFIG_SYS_MAX_FLASH_SECT 512
91
92
93#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) \
94 | BR_MS_GPCM \
95 | BR_PS_32 \
96 | BR_V)
97
98
99#define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT \
100 | OR_GPCM_ACS_DIV4 \
101 | OR_GPCM_SCY_5 \
102 | OR_GPCM_TRLX)
103
104#define CONFIG_SYS_PRELIM_OR_AM OR_AM_1GB
105
106#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \
107 | CONFIG_SYS_OR_TIMING_FLASH)
108
109#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_1GB)
110
111
112#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
113
114
115#define CONFIG_SYS_BR1_PRELIM 0x00000000
116#define CONFIG_SYS_OR1_PRELIM 0x00000000
117#define CONFIG_SYS_LBLAWBAR1_PRELIM 0x00000000
118#define CONFIG_SYS_LBLAWAR1_PRELIM 0x00000000
119
120#define CONFIG_SYS_BR2_PRELIM 0x00000000
121#define CONFIG_SYS_OR2_PRELIM 0x00000000
122#define CONFIG_SYS_LBLAWBAR2_PRELIM 0x00000000
123#define CONFIG_SYS_LBLAWAR2_PRELIM 0x00000000
124
125#define CONFIG_SYS_BR3_PRELIM 0x00000000
126#define CONFIG_SYS_OR3_PRELIM 0x00000000
127#define CONFIG_SYS_LBLAWBAR3_PRELIM 0x00000000
128#define CONFIG_SYS_LBLAWAR3_PRELIM 0x00000000
129
130
131
132
133#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
134
135#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
136# define CONFIG_SYS_RAMBOOT
137#else
138# undef CONFIG_SYS_RAMBOOT
139#endif
140
141#define CONFIG_SYS_INIT_RAM_LOCK 1
142#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
143#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
144
145#define CONFIG_SYS_GBL_DATA_OFFSET \
146 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
147#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
148
149
150#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
151
152#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
153
154
155
156
157#define CONFIG_CONS_INDEX 1
158#define CONFIG_SYS_NS16550_SERIAL
159#define CONFIG_SYS_NS16550_REG_SIZE 1
160#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
161
162#define CONFIG_SYS_BAUDRATE_TABLE \
163 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
164
165#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
166#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
167
168
169
170
171#define CONFIG_SYS_I2C
172#define CONFIG_SYS_I2C_FSL
173#define CONFIG_SYS_FSL_I2C_SPEED 400000
174#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
175#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
176
177
178#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
179#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
180#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
181#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12
182
183
184#define CONFIG_RTC_DS1337
185#define CONFIG_SYS_I2C_RTC_ADDR 0x68
186
187
188#define CONFIG_DTT_LM75 1
189#define CONFIG_DTT_SENSORS {0}
190#define CONFIG_SYS_DTT_MAX_TEMP 70
191#define CONFIG_SYS_DTT_LOW_TEMP -30
192#define CONFIG_SYS_DTT_HYSTERESIS 3
193
194
195
196
197#define CONFIG_TSEC_ENET
198#define CONFIG_MII
199
200#define CONFIG_SYS_TSEC1_OFFSET 0x24000
201#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
202#define CONFIG_SYS_TSEC2_OFFSET 0x25000
203#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
204
205#if defined(CONFIG_TSEC_ENET)
206
207#define CONFIG_TSEC1 1
208#define CONFIG_TSEC1_NAME "TSEC0"
209#define CONFIG_TSEC2 1
210#define CONFIG_TSEC2_NAME "TSEC1"
211#define TSEC1_PHY_ADDR 2
212#define TSEC2_PHY_ADDR 1
213#define TSEC1_PHYIDX 0
214#define TSEC2_PHYIDX 0
215#define TSEC1_FLAGS TSEC_GIGABIT
216#define TSEC2_FLAGS TSEC_GIGABIT
217
218
219#define CONFIG_ETHPRIME "TSEC0"
220
221#endif
222
223
224
225
226
227
228#if defined(CONFIG_PCI)
229
230#define CONFIG_PCI_SCAN_SHOW
231
232
233#define CONFIG_SYS_PCI1_MEM_BASE 0x90000000
234#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
235#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
236#define CONFIG_SYS_PCI1_MMIO_BASE \
237 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
238#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
239#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
240#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
241#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
242#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000
243
244#undef CONFIG_EEPRO100
245#define CONFIG_EEPRO100
246#undef CONFIG_TULIP
247
248#if !defined(CONFIG_PCI_PNP)
249 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE
250 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE
251 #define PCI_IDSEL_NUMBER 0x1c
252#endif
253
254#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957
255
256#endif
257
258
259
260
261#define CONFIG_ENV_IS_IN_FLASH 1
262#define CONFIG_ENV_ADDR \
263 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
264#define CONFIG_ENV_SECT_SIZE 0x20000
265#define CONFIG_ENV_SIZE 0x8000
266#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
267#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
268
269#define CONFIG_LOADS_ECHO 1
270#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
271
272
273
274
275#define CONFIG_BOOTP_BOOTFILESIZE
276#define CONFIG_BOOTP_BOOTPATH
277#define CONFIG_BOOTP_GATEWAY
278#define CONFIG_BOOTP_HOSTNAME
279
280
281
282
283#define CONFIG_CMD_DATE
284#define CONFIG_CMD_DTT
285#define CONFIG_CMD_EEPROM
286#define CONFIG_CMD_JFFS2
287#define CONFIG_CMD_REGINFO
288
289#if defined(CONFIG_PCI)
290 #define CONFIG_CMD_PCI
291#endif
292
293
294
295
296#define CONFIG_SYS_LONGHELP
297#define CONFIG_SYS_LOAD_ADDR 0x2000000
298
299#define CONFIG_CMDLINE_EDITING 1
300#define CONFIG_AUTO_COMPLETE
301
302#if defined(CONFIG_CMD_KGDB)
303 #define CONFIG_SYS_CBSIZE 1024
304#else
305 #define CONFIG_SYS_CBSIZE 256
306#endif
307
308
309#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
310#define CONFIG_SYS_MAXARGS 16
311
312#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
313
314#undef CONFIG_WATCHDOG
315
316
317
318
319
320
321
322#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
323
324#define CONFIG_SYS_HRCW_LOW (\
325 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
326 HRCWL_DDR_TO_SCB_CLK_1X1 |\
327 HRCWL_CSB_TO_CLKIN_4X1 |\
328 HRCWL_VCO_1X2 |\
329 HRCWL_CORE_TO_CSB_2X1)
330
331#if defined(PCI_64BIT)
332#define CONFIG_SYS_HRCW_HIGH (\
333 HRCWH_PCI_HOST |\
334 HRCWH_64_BIT_PCI |\
335 HRCWH_PCI1_ARBITER_ENABLE |\
336 HRCWH_PCI2_ARBITER_DISABLE |\
337 HRCWH_CORE_ENABLE |\
338 HRCWH_FROM_0X00000100 |\
339 HRCWH_BOOTSEQ_DISABLE |\
340 HRCWH_SW_WATCHDOG_DISABLE |\
341 HRCWH_ROM_LOC_LOCAL_16BIT |\
342 HRCWH_TSEC1M_IN_GMII |\
343 HRCWH_TSEC2M_IN_GMII)
344#else
345#define CONFIG_SYS_HRCW_HIGH (\
346 HRCWH_PCI_HOST |\
347 HRCWH_32_BIT_PCI |\
348 HRCWH_PCI1_ARBITER_ENABLE |\
349 HRCWH_PCI2_ARBITER_DISABLE |\
350 HRCWH_CORE_ENABLE |\
351 HRCWH_FROM_0X00000100 |\
352 HRCWH_BOOTSEQ_DISABLE |\
353 HRCWH_SW_WATCHDOG_DISABLE |\
354 HRCWH_ROM_LOC_LOCAL_16BIT |\
355 HRCWH_TSEC1M_IN_GMII |\
356 HRCWH_TSEC2M_IN_GMII)
357#endif
358
359
360#define CONFIG_SYS_SICRH 0
361#define CONFIG_SYS_SICRL SICRL_LDP_A
362
363
364#define CONFIG_SYS_HID0_INIT 0x000000000
365#define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \
366 HID0_ENABLE_INSTRUCTION_CACHE)
367#define CONFIG_SYS_HID2 HID2_HBE
368
369#define CONFIG_HIGH_BATS 1
370
371
372#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
373 | BATL_PP_RW \
374 | BATL_MEMCOHERENCE)
375#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
376 | BATU_BL_256M \
377 | BATU_VS \
378 | BATU_VP)
379#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
380 | BATL_PP_RW \
381 | BATL_MEMCOHERENCE)
382#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
383 | BATU_BL_256M \
384 | BATU_VS \
385 | BATU_VP)
386
387
388#define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR \
389 | BATL_PP_RW \
390 | BATL_MEMCOHERENCE)
391#define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR \
392 | BATU_BL_128K \
393 | BATU_VS \
394 | BATU_VP)
395
396
397#ifdef CONFIG_PCI
398#define CONFIG_PCI_INDIRECT_BRIDGE
399#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE \
400 | BATL_PP_RW \
401 | BATL_MEMCOHERENCE)
402#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE \
403 | BATU_BL_256M \
404 | BATU_VS \
405 | BATU_VP)
406#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE \
407 | BATL_PP_RW \
408 | BATL_MEMCOHERENCE \
409 | BATL_GUARDEDSTORAGE)
410#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE \
411 | BATU_BL_256M \
412 | BATU_VS \
413 | BATU_VP)
414#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE \
415 | BATL_PP_RW \
416 | BATL_CACHEINHIBIT \
417 | BATL_GUARDEDSTORAGE)
418#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE \
419 | BATU_BL_16M \
420 | BATU_VS \
421 | BATU_VP)
422#else
423#define CONFIG_SYS_IBAT3L (0)
424#define CONFIG_SYS_IBAT3U (0)
425#define CONFIG_SYS_IBAT4L (0)
426#define CONFIG_SYS_IBAT4U (0)
427#define CONFIG_SYS_IBAT5L (0)
428#define CONFIG_SYS_IBAT5U (0)
429#endif
430
431
432#define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR \
433 | BATL_PP_RW \
434 | BATL_CACHEINHIBIT \
435 | BATL_GUARDEDSTORAGE)
436#define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR \
437 | BATU_BL_1M \
438 | BATU_VS \
439 | BATU_VP)
440
441
442#define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE \
443 | BATL_PP_RW \
444 | BATL_CACHEINHIBIT \
445 | BATL_GUARDEDSTORAGE)
446#define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE \
447 | BATU_BL_256M \
448 | BATU_VS \
449 | BATU_VP)
450
451#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
452#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
453#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
454#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
455#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
456#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
457#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
458#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
459#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
460#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
461#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
462#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
463#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
464#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
465#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
466#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
467
468#if defined(CONFIG_CMD_KGDB)
469#define CONFIG_KGDB_BAUDRATE 230400
470#endif
471
472
473
474
475
476
477#define CONFIG_LOADADDR 400000
478
479#undef CONFIG_BOOTARGS
480
481#define CONFIG_BAUDRATE 115200
482
483#define CONFIG_PREBOOT "echo;" \
484 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
485 "echo"
486
487#undef CONFIG_BOOTARGS
488
489#define CONFIG_EXTRA_ENV_SETTINGS \
490 "netdev=eth0\0" \
491 "hostname=tqm834x\0" \
492 "nfsargs=setenv bootargs root=/dev/nfs rw " \
493 "nfsroot=${serverip}:${rootpath}\0" \
494 "ramargs=setenv bootargs root=/dev/ram rw\0" \
495 "addip=setenv bootargs ${bootargs} " \
496 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
497 ":${hostname}:${netdev}:off panic=1\0" \
498 "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
499 "flash_nfs_old=run nfsargs addip addcons;" \
500 "bootm ${kernel_addr}\0" \
501 "flash_nfs=run nfsargs addip addcons;" \
502 "bootm ${kernel_addr} - ${fdt_addr}\0" \
503 "flash_self_old=run ramargs addip addcons;" \
504 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
505 "flash_self=run ramargs addip addcons;" \
506 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
507 "net_nfs_old=tftp 400000 ${bootfile};" \
508 "run nfsargs addip addcons;bootm\0" \
509 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
510 "tftp ${fdt_addr_r} ${fdt_file}; " \
511 "run nfsargs addip addcons; " \
512 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
513 "rootpath=/opt/eldk/ppc_6xx\0" \
514 "bootfile=tqm834x/uImage\0" \
515 "fdtfile=tqm834x/tqm834x.dtb\0" \
516 "kernel_addr_r=400000\0" \
517 "fdt_addr_r=600000\0" \
518 "ramdisk_addr_r=800000\0" \
519 "kernel_addr=800C0000\0" \
520 "fdt_addr=800A0000\0" \
521 "ramdisk_addr=80300000\0" \
522 "u-boot=tqm834x/u-boot.bin\0" \
523 "load=tftp 200000 ${u-boot}\0" \
524 "update=protect off 80000000 +${filesize};" \
525 "era 80000000 +${filesize};" \
526 "cp.b 200000 80000000 ${filesize}\0" \
527 "upd=run load update\0" \
528 ""
529
530#define CONFIG_BOOTCOMMAND "run flash_self"
531
532
533
534
535
536#define CONFIG_CMD_MTDPARTS
537#define CONFIG_MTD_DEVICE
538#define CONFIG_FLASH_CFI_MTD
539#define MTDIDS_DEFAULT "nor0=TQM834x-0"
540
541
542#define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),256k(env)," \
543 "1m(kernel),2m(initrd)," \
544 "-(user);" \
545
546#endif
547