1/* 2 * (C) Copyright 2000-2014 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* 9 * board/config.h - configuration options, board specific 10 */ 11 12#ifndef __CONFIG_H 13#define __CONFIG_H 14 15/* 16 * High Level Configuration Options 17 * (easy to change) 18 */ 19 20#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ 21#define CONFIG_TQM850M 1 /* ...on a TQM8xxM module */ 22 23#define CONFIG_SYS_TEXT_BASE 0x40000000 24 25#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 26#define CONFIG_SYS_SMC_RXBUFLEN 128 27#define CONFIG_SYS_MAXIDLE 10 28#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 29 30#define CONFIG_BOOTCOUNT_LIMIT 31 32 33#define CONFIG_BOARD_TYPES 1 /* support board types */ 34 35#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" 36 37#undef CONFIG_BOOTARGS 38 39#define CONFIG_EXTRA_ENV_SETTINGS \ 40 "netdev=eth0\0" \ 41 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 42 "nfsroot=${serverip}:${rootpath}\0" \ 43 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 44 "addip=setenv bootargs ${bootargs} " \ 45 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 46 ":${hostname}:${netdev}:off panic=1\0" \ 47 "flash_nfs=run nfsargs addip;" \ 48 "bootm ${kernel_addr}\0" \ 49 "flash_self=run ramargs addip;" \ 50 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 51 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 52 "rootpath=/opt/eldk/ppc_8xx\0" \ 53 "hostname=TQM850M\0" \ 54 "bootfile=TQM850M/uImage\0" \ 55 "fdt_addr=40080000\0" \ 56 "kernel_addr=400A0000\0" \ 57 "ramdisk_addr=40280000\0" \ 58 "u-boot=TQM850M/u-image.bin\0" \ 59 "load=tftp 200000 ${u-boot}\0" \ 60 "update=prot off 40000000 +${filesize};" \ 61 "era 40000000 +${filesize};" \ 62 "cp.b 200000 40000000 ${filesize};" \ 63 "sete filesize;save\0" \ 64 "" 65#define CONFIG_BOOTCOMMAND "run flash_self" 66 67#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 68#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 69 70#undef CONFIG_WATCHDOG /* watchdog disabled */ 71 72#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 73 74/* 75 * BOOTP options 76 */ 77#define CONFIG_BOOTP_SUBNETMASK 78#define CONFIG_BOOTP_GATEWAY 79#define CONFIG_BOOTP_HOSTNAME 80#define CONFIG_BOOTP_BOOTPATH 81#define CONFIG_BOOTP_BOOTFILESIZE 82 83#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 84 85/* 86 * Command line configuration. 87 */ 88#define CONFIG_CMD_DATE 89#define CONFIG_CMD_IDE 90#define CONFIG_CMD_JFFS2 91 92#define CONFIG_NETCONSOLE 93 94/* 95 * Miscellaneous configurable options 96 */ 97#define CONFIG_SYS_LONGHELP /* undef to save memory */ 98 99#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 100 101#if defined(CONFIG_CMD_KGDB) 102#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 103#else 104#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 105#endif 106#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 107#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 108#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 109 110#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 111#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 112 113#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 114 115/* 116 * Low Level Configuration Settings 117 * (address mappings, register initial values, etc.) 118 * You should know what you are doing if you make changes here. 119 */ 120/*----------------------------------------------------------------------- 121 * Internal Memory Mapped Register 122 */ 123#define CONFIG_SYS_IMMR 0xFFF00000 124 125/*----------------------------------------------------------------------- 126 * Definitions for initial stack pointer and data area (in DPRAM) 127 */ 128#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 129#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 130#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 131#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 132 133/*----------------------------------------------------------------------- 134 * Start addresses for the final memory configuration 135 * (Set up by the startup code) 136 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 137 */ 138#define CONFIG_SYS_SDRAM_BASE 0x00000000 139#define CONFIG_SYS_FLASH_BASE 0x40000000 140#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 141#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 142#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 143 144/* 145 * For booting Linux, the board info and command line data 146 * have to be in the first 8 MB of memory, since this is 147 * the maximum mapped by the Linux kernel during initialization. 148 */ 149#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 150 151/*----------------------------------------------------------------------- 152 * FLASH organization 153 */ 154 155/* use CFI flash driver */ 156#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 157#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 158#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 159#define CONFIG_SYS_FLASH_EMPTY_INFO 160#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 161#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 162#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 163 164#define CONFIG_ENV_IS_IN_FLASH 1 165#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ 166#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ 167#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ 168 169/* Address and size of Redundant Environment Sector */ 170#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) 171#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 172 173#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 174 175#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 176 177/*----------------------------------------------------------------------- 178 * Dynamic MTD partition support 179 */ 180#define CONFIG_CMD_MTDPARTS 181#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 182#define CONFIG_FLASH_CFI_MTD 183#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" 184 185#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ 186 "128k(dtb)," \ 187 "1920k(kernel)," \ 188 "5632(rootfs)," \ 189 "4m(data)" 190 191/*----------------------------------------------------------------------- 192 * Hardware Information Block 193 */ 194#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 195#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 196#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 197 198/*----------------------------------------------------------------------- 199 * Cache Configuration 200 */ 201#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 202#if defined(CONFIG_CMD_KGDB) 203#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 204#endif 205 206/*----------------------------------------------------------------------- 207 * SYPCR - System Protection Control 11-9 208 * SYPCR can only be written once after reset! 209 *----------------------------------------------------------------------- 210 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 211 */ 212#if defined(CONFIG_WATCHDOG) 213#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 214 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 215#else 216#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 217#endif 218 219/*----------------------------------------------------------------------- 220 * SIUMCR - SIU Module Configuration 11-6 221 *----------------------------------------------------------------------- 222 * PCMCIA config., multi-function pin tri-state 223 */ 224#ifndef CONFIG_CAN_DRIVER 225#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 226#else /* we must activate GPL5 in the SIUMCR for CAN */ 227#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 228#endif /* CONFIG_CAN_DRIVER */ 229 230/*----------------------------------------------------------------------- 231 * TBSCR - Time Base Status and Control 11-26 232 *----------------------------------------------------------------------- 233 * Clear Reference Interrupt Status, Timebase freezing enabled 234 */ 235#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 236 237/*----------------------------------------------------------------------- 238 * RTCSC - Real-Time Clock Status and Control Register 11-27 239 *----------------------------------------------------------------------- 240 */ 241#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 242 243/*----------------------------------------------------------------------- 244 * PISCR - Periodic Interrupt Status and Control 11-31 245 *----------------------------------------------------------------------- 246 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 247 */ 248#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 249 250/*----------------------------------------------------------------------- 251 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 252 *----------------------------------------------------------------------- 253 * Reset PLL lock status sticky bit, timer expired status bit and timer 254 * interrupt status bit 255 */ 256#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 257 258/*----------------------------------------------------------------------- 259 * SCCR - System Clock and reset Control Register 15-27 260 *----------------------------------------------------------------------- 261 * Set clock output, timebase and RTC source and divider, 262 * power management and some other internal clocks 263 */ 264#define SCCR_MASK SCCR_EBDF11 265#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 266 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 267 SCCR_DFALCD00) 268 269/*----------------------------------------------------------------------- 270 * PCMCIA stuff 271 *----------------------------------------------------------------------- 272 * 273 */ 274#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 275#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 276#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 277#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 278#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 279#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 280#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 281#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 282 283/*----------------------------------------------------------------------- 284 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 285 *----------------------------------------------------------------------- 286 */ 287 288#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ 289#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 290 291#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 292#undef CONFIG_IDE_LED /* LED for ide not supported */ 293#undef CONFIG_IDE_RESET /* reset for ide not supported */ 294 295#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 296#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 297 298#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 299 300#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 301 302/* Offset for data I/O */ 303#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 304 305/* Offset for normal register accesses */ 306#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 307 308/* Offset for alternate registers */ 309#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 310 311/*----------------------------------------------------------------------- 312 * 313 *----------------------------------------------------------------------- 314 * 315 */ 316#define CONFIG_SYS_DER 0 317 318/* 319 * Init Memory Controller: 320 * 321 * BR0/1 and OR0/1 (FLASH) 322 */ 323 324#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 325#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 326 327/* used to re-map FLASH both when starting from SRAM or FLASH: 328 * restrict access enough to keep SRAM working (if any) 329 * but not too much to meddle with FLASH accesses 330 */ 331#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 332#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 333 334/* 335 * FLASH timing: 336 */ 337#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 338 OR_SCY_3_CLK | OR_EHTR | OR_BI) 339 340#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 341#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 342#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 343 344#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 345#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 346#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 347 348/* 349 * BR2/3 and OR2/3 (SDRAM) 350 * 351 */ 352#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 353#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 354#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 355 356/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 357#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 358 359#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 360#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 361 362#ifndef CONFIG_CAN_DRIVER 363#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 364#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 365#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 366#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 367#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 368#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 369#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 370 BR_PS_8 | BR_MS_UPMB | BR_V ) 371#endif /* CONFIG_CAN_DRIVER */ 372 373/* 374 * Memory Periodic Timer Prescaler 375 * 376 * The Divider for PTA (refresh timer) configuration is based on an 377 * example SDRAM configuration (64 MBit, one bank). The adjustment to 378 * the number of chip selects (NCS) and the actually needed refresh 379 * rate is done by setting MPTPR. 380 * 381 * PTA is calculated from 382 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 383 * 384 * gclk CPU clock (not bus clock!) 385 * Trefresh Refresh cycle * 4 (four word bursts used) 386 * 387 * 4096 Rows from SDRAM example configuration 388 * 1000 factor s -> ms 389 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 390 * 4 Number of refresh cycles per period 391 * 64 Refresh cycle in ms per number of rows 392 * -------------------------------------------- 393 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 394 * 395 * 50 MHz => 50.000.000 / Divider = 98 396 * 66 Mhz => 66.000.000 / Divider = 129 397 * 80 Mhz => 80.000.000 / Divider = 156 398 */ 399 400#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 401#define CONFIG_SYS_MAMR_PTA 98 402 403/* 404 * For 16 MBit, refresh rates could be 31.3 us 405 * (= 64 ms / 2K = 125 / quad bursts). 406 * For a simpler initialization, 15.6 us is used instead. 407 * 408 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 409 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 410 */ 411#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 412#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 413 414/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 415#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 416#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 417 418/* 419 * MAMR settings for SDRAM 420 */ 421 422/* 8 column SDRAM */ 423#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 424 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 425 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 426/* 9 column SDRAM */ 427#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 428 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 429 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 430 431#define CONFIG_HWCONFIG 1 432 433#endif /* __CONFIG_H */ 434