1/* 2 * (C) Copyright 2000-2014 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* 9 * board/config.h - configuration options, board specific 10 */ 11 12#ifndef __CONFIG_H 13#define __CONFIG_H 14 15/* 16 * High Level Configuration Options 17 * (easy to change) 18 */ 19 20#define CONFIG_MPC855 1 /* This is a MPC855 CPU */ 21#define CONFIG_TQM855L 1 /* ...on a TQM8xxL module */ 22 23#define CONFIG_SYS_TEXT_BASE 0x40000000 24 25#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 26#define CONFIG_SYS_SMC_RXBUFLEN 128 27#define CONFIG_SYS_MAXIDLE 10 28#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 29 30#define CONFIG_BOOTCOUNT_LIMIT 31 32 33#define CONFIG_BOARD_TYPES 1 /* support board types */ 34 35#define CONFIG_PREBOOT "echo;" \ 36 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 37 "echo" 38 39#undef CONFIG_BOOTARGS 40 41#define CONFIG_EXTRA_ENV_SETTINGS \ 42 "netdev=eth0\0" \ 43 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 44 "nfsroot=${serverip}:${rootpath}\0" \ 45 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 46 "addip=setenv bootargs ${bootargs} " \ 47 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 48 ":${hostname}:${netdev}:off panic=1\0" \ 49 "flash_nfs=run nfsargs addip;" \ 50 "bootm ${kernel_addr}\0" \ 51 "flash_self=run ramargs addip;" \ 52 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 53 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 54 "rootpath=/opt/eldk/ppc_8xx\0" \ 55 "hostname=TQM855L\0" \ 56 "bootfile=TQM855L/uImage\0" \ 57 "fdt_addr=40040000\0" \ 58 "kernel_addr=40060000\0" \ 59 "ramdisk_addr=40200000\0" \ 60 "u-boot=TQM855L/u-image.bin\0" \ 61 "load=tftp 200000 ${u-boot}\0" \ 62 "update=prot off 40000000 +${filesize};" \ 63 "era 40000000 +${filesize};" \ 64 "cp.b 200000 40000000 ${filesize};" \ 65 "sete filesize;save\0" \ 66 "" 67#define CONFIG_BOOTCOMMAND "run flash_self" 68 69#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 70#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 71 72#undef CONFIG_WATCHDOG /* watchdog disabled */ 73 74#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 75 76/* 77 * BOOTP options 78 */ 79#define CONFIG_BOOTP_SUBNETMASK 80#define CONFIG_BOOTP_GATEWAY 81#define CONFIG_BOOTP_HOSTNAME 82#define CONFIG_BOOTP_BOOTPATH 83#define CONFIG_BOOTP_BOOTFILESIZE 84 85#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 86 87/* 88 * Command line configuration. 89 */ 90#define CONFIG_CMD_DATE 91#define CONFIG_CMD_IDE 92#define CONFIG_CMD_JFFS2 93 94#define CONFIG_NETCONSOLE 95 96/* 97 * Miscellaneous configurable options 98 */ 99#define CONFIG_SYS_LONGHELP /* undef to save memory */ 100 101#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 102 103#if defined(CONFIG_CMD_KGDB) 104#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 105#else 106#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 107#endif 108#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 109#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 110#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 111 112#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 113#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 114 115#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 116 117/* 118 * Low Level Configuration Settings 119 * (address mappings, register initial values, etc.) 120 * You should know what you are doing if you make changes here. 121 */ 122/*----------------------------------------------------------------------- 123 * Internal Memory Mapped Register 124 */ 125#define CONFIG_SYS_IMMR 0xFFF00000 126 127/*----------------------------------------------------------------------- 128 * Definitions for initial stack pointer and data area (in DPRAM) 129 */ 130#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 131#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 132#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 133#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 134 135/*----------------------------------------------------------------------- 136 * Start addresses for the final memory configuration 137 * (Set up by the startup code) 138 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 139 */ 140#define CONFIG_SYS_SDRAM_BASE 0x00000000 141#define CONFIG_SYS_FLASH_BASE 0x40000000 142#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 143#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 144#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 145 146/* 147 * For booting Linux, the board info and command line data 148 * have to be in the first 8 MB of memory, since this is 149 * the maximum mapped by the Linux kernel during initialization. 150 */ 151#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 152 153/*----------------------------------------------------------------------- 154 * FLASH organization 155 */ 156 157/* use CFI flash driver */ 158#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 159#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 160#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } 161#define CONFIG_SYS_FLASH_EMPTY_INFO 162#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 163#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 164#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ 165 166#define CONFIG_ENV_IS_IN_FLASH 1 167#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ 168#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ 169 170/* Address and size of Redundant Environment Sector */ 171#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) 172#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 173 174#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 175 176#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 177 178/*----------------------------------------------------------------------- 179 * Dynamic MTD partition support 180 */ 181#define CONFIG_CMD_MTDPARTS 182#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 183#define CONFIG_FLASH_CFI_MTD 184#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" 185 186#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ 187 "128k(dtb)," \ 188 "1664k(kernel)," \ 189 "2m(rootfs)," \ 190 "4m(data)" 191 192/*----------------------------------------------------------------------- 193 * Hardware Information Block 194 */ 195#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 196#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 197#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 198 199/*----------------------------------------------------------------------- 200 * Cache Configuration 201 */ 202#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 203#if defined(CONFIG_CMD_KGDB) 204#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 205#endif 206 207/*----------------------------------------------------------------------- 208 * SYPCR - System Protection Control 11-9 209 * SYPCR can only be written once after reset! 210 *----------------------------------------------------------------------- 211 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 212 */ 213#if defined(CONFIG_WATCHDOG) 214#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 215 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 216#else 217#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 218#endif 219 220/*----------------------------------------------------------------------- 221 * SIUMCR - SIU Module Configuration 11-6 222 *----------------------------------------------------------------------- 223 * PCMCIA config., multi-function pin tri-state 224 */ 225#ifndef CONFIG_CAN_DRIVER 226#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 227#else /* we must activate GPL5 in the SIUMCR for CAN */ 228#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 229#endif /* CONFIG_CAN_DRIVER */ 230 231/*----------------------------------------------------------------------- 232 * TBSCR - Time Base Status and Control 11-26 233 *----------------------------------------------------------------------- 234 * Clear Reference Interrupt Status, Timebase freezing enabled 235 */ 236#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 237 238/*----------------------------------------------------------------------- 239 * RTCSC - Real-Time Clock Status and Control Register 11-27 240 *----------------------------------------------------------------------- 241 */ 242#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 243 244/*----------------------------------------------------------------------- 245 * PISCR - Periodic Interrupt Status and Control 11-31 246 *----------------------------------------------------------------------- 247 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 248 */ 249#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 250 251/*----------------------------------------------------------------------- 252 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 253 *----------------------------------------------------------------------- 254 * Reset PLL lock status sticky bit, timer expired status bit and timer 255 * interrupt status bit 256 */ 257#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 258 259/*----------------------------------------------------------------------- 260 * SCCR - System Clock and reset Control Register 15-27 261 *----------------------------------------------------------------------- 262 * Set clock output, timebase and RTC source and divider, 263 * power management and some other internal clocks 264 */ 265#define SCCR_MASK SCCR_EBDF11 266#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 267 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 268 SCCR_DFALCD00) 269 270/*----------------------------------------------------------------------- 271 * PCMCIA stuff 272 *----------------------------------------------------------------------- 273 * 274 */ 275#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 276#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 277#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 278#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 279#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 280#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 281#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 282#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 283 284/*----------------------------------------------------------------------- 285 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 286 *----------------------------------------------------------------------- 287 */ 288 289#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ 290#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 291 292#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 293#undef CONFIG_IDE_LED /* LED for ide not supported */ 294#undef CONFIG_IDE_RESET /* reset for ide not supported */ 295 296#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 297#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 298 299#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 300 301#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 302 303/* Offset for data I/O */ 304#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 305 306/* Offset for normal register accesses */ 307#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 308 309/* Offset for alternate registers */ 310#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 311 312/*----------------------------------------------------------------------- 313 * 314 *----------------------------------------------------------------------- 315 * 316 */ 317#define CONFIG_SYS_DER 0 318 319/* 320 * Init Memory Controller: 321 * 322 * BR0/1 and OR0/1 (FLASH) 323 */ 324 325#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 326#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 327 328/* used to re-map FLASH both when starting from SRAM or FLASH: 329 * restrict access enough to keep SRAM working (if any) 330 * but not too much to meddle with FLASH accesses 331 */ 332#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 333#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 334 335/* 336 * FLASH timing: 337 */ 338#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 339 OR_SCY_3_CLK | OR_EHTR | OR_BI) 340 341#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 342#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 343#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 344 345#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 346#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 347#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 348 349/* 350 * BR2/3 and OR2/3 (SDRAM) 351 * 352 */ 353#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 354#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 355#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 356 357/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 358#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 359 360#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 361#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 362 363#ifndef CONFIG_CAN_DRIVER 364#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 365#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 366#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 367#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 368#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 369#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 370#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 371 BR_PS_8 | BR_MS_UPMB | BR_V ) 372#endif /* CONFIG_CAN_DRIVER */ 373 374/* 375 * Memory Periodic Timer Prescaler 376 * 377 * The Divider for PTA (refresh timer) configuration is based on an 378 * example SDRAM configuration (64 MBit, one bank). The adjustment to 379 * the number of chip selects (NCS) and the actually needed refresh 380 * rate is done by setting MPTPR. 381 * 382 * PTA is calculated from 383 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 384 * 385 * gclk CPU clock (not bus clock!) 386 * Trefresh Refresh cycle * 4 (four word bursts used) 387 * 388 * 4096 Rows from SDRAM example configuration 389 * 1000 factor s -> ms 390 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 391 * 4 Number of refresh cycles per period 392 * 64 Refresh cycle in ms per number of rows 393 * -------------------------------------------- 394 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 395 * 396 * 50 MHz => 50.000.000 / Divider = 98 397 * 66 Mhz => 66.000.000 / Divider = 129 398 * 80 Mhz => 80.000.000 / Divider = 156 399 */ 400 401#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 402#define CONFIG_SYS_MAMR_PTA 98 403 404/* 405 * For 16 MBit, refresh rates could be 31.3 us 406 * (= 64 ms / 2K = 125 / quad bursts). 407 * For a simpler initialization, 15.6 us is used instead. 408 * 409 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 410 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 411 */ 412#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 413#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 414 415/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 416#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 417#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 418 419/* 420 * MAMR settings for SDRAM 421 */ 422 423/* 8 column SDRAM */ 424#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 425 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 426 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 427/* 9 column SDRAM */ 428#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 429 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 430 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 431 432#define CONFIG_SCC1_ENET 433#define CONFIG_FEC_ENET 434#define CONFIG_ETHPRIME "SCC" 435 436#define CONFIG_HWCONFIG 1 437 438#endif /* __CONFIG_H */ 439