1/* 2 * (C) Copyright 2000-2014 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * (C) Copyright 2006 6 * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11/* 12 * board/config.h - configuration options, board specific 13 */ 14 15#ifndef __CONFIG_H 16#define __CONFIG_H 17 18/* 19 * High Level Configuration Options 20 * (easy to change) 21 */ 22 23#define CONFIG_MPC885 1 /* This is a MPC885 CPU */ 24#define CONFIG_TQM885D 1 /* ...on a TQM88D module */ 25 26#define CONFIG_SYS_TEXT_BASE 0x40000000 27 28#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ 29#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ 30#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ 31#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 66 MHz - CPU default clock */ 32 /* (it will be used if there is no */ 33 /* 'cpuclk' variable with valid value) */ 34 35#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 36#define CONFIG_SYS_SMC_RXBUFLEN 128 37#define CONFIG_SYS_MAXIDLE 10 38#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 39 40#define CONFIG_BOOTCOUNT_LIMIT 41 42 43#define CONFIG_BOARD_TYPES 1 /* support board types */ 44 45#define CONFIG_PREBOOT "echo;" \ 46 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 47 "echo" 48 49#undef CONFIG_BOOTARGS 50 51#define CONFIG_EXTRA_ENV_SETTINGS \ 52 "netdev=eth0\0" \ 53 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 54 "nfsroot=${serverip}:${rootpath}\0" \ 55 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 56 "addip=setenv bootargs ${bootargs} " \ 57 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 58 ":${hostname}:${netdev}:off panic=1\0" \ 59 "flash_nfs=run nfsargs addip;" \ 60 "bootm ${kernel_addr}\0" \ 61 "flash_self=run ramargs addip;" \ 62 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 63 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 64 "rootpath=/opt/eldk/ppc_8xx\0" \ 65 "bootfile=/tftpboot/TQM885D/uImage\0" \ 66 "fdt_addr=400C0000\0" \ 67 "kernel_addr=40100000\0" \ 68 "ramdisk_addr=40280000\0" \ 69 "load=tftp 200000 ${u-boot}\0" \ 70 "update=protect off 40000000 +${filesize};" \ 71 "erase 40000000 +${filesize};" \ 72 "cp.b 200000 40000000 ${filesize};" \ 73 "protect on 40000000 +${filesize}\0" \ 74 "" 75#define CONFIG_BOOTCOMMAND "run flash_self" 76 77#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 78#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 79 80#undef CONFIG_WATCHDOG /* watchdog disabled */ 81 82#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 83 84/* enable I2C and select the hardware/software driver */ 85#define CONFIG_SYS_I2C 86#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ 87#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */ 88#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE 89/* 90 * Software (bit-bang) I2C driver configuration 91 */ 92#define PB_SCL 0x00000020 /* PB 26 */ 93#define PB_SDA 0x00000010 /* PB 27 */ 94 95#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) 96#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) 97#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) 98#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) 99#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ 100 else immr->im_cpm.cp_pbdat &= ~PB_SDA 101#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ 102 else immr->im_cpm.cp_pbdat &= ~PB_SCL 103#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ 104 105#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */ 106#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ 107#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 108#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ 109 110# define CONFIG_RTC_DS1337 1 111# define CONFIG_SYS_I2C_RTC_ADDR 0x68 112 113/* 114 * BOOTP options 115 */ 116#define CONFIG_BOOTP_SUBNETMASK 117#define CONFIG_BOOTP_GATEWAY 118#define CONFIG_BOOTP_HOSTNAME 119#define CONFIG_BOOTP_BOOTPATH 120#define CONFIG_BOOTP_BOOTFILESIZE 121 122#undef CONFIG_RTC_MPC8xx /* MPC885 does not support RTC */ 123 124#define CONFIG_TIMESTAMP /* but print image timestmps */ 125 126/* 127 * Command line configuration. 128 */ 129#define CONFIG_CMD_DATE 130#define CONFIG_CMD_EEPROM 131#define CONFIG_CMD_IDE 132 133/* 134 * Miscellaneous configurable options 135 */ 136#define CONFIG_SYS_LONGHELP /* undef to save memory */ 137 138#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 139 140#if defined(CONFIG_CMD_KGDB) 141#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 142#else 143#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 144#endif 145#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 146#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 147#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 148 149#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ 150#define CONFIG_SYS_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */ 151#define CONFIG_SYS_ALT_MEMTEST /* alternate, more extensive 152 memory test.*/ 153 154#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 155 156/* 157 * Low Level Configuration Settings 158 * (address mappings, register initial values, etc.) 159 * You should know what you are doing if you make changes here. 160 */ 161/*----------------------------------------------------------------------- 162 * Internal Memory Mapped Register 163 */ 164#define CONFIG_SYS_IMMR 0xFFF00000 165 166/*----------------------------------------------------------------------- 167 * Definitions for initial stack pointer and data area (in DPRAM) 168 */ 169#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 170#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 171#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 172#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 173 174/*----------------------------------------------------------------------- 175 * Start addresses for the final memory configuration 176 * (Set up by the startup code) 177 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 178 */ 179#define CONFIG_SYS_SDRAM_BASE 0x00000000 180#define CONFIG_SYS_FLASH_BASE 0x40000000 181#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 182#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 183#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */ 184 185/* 186 * For booting Linux, the board info and command line data 187 * have to be in the first 8 MB of memory, since this is 188 * the maximum mapped by the Linux kernel during initialization. 189 */ 190#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 191 192/*----------------------------------------------------------------------- 193 * FLASH organization 194 */ 195 196/* use CFI flash driver */ 197#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 198#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 199#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 200#define CONFIG_SYS_FLASH_EMPTY_INFO 201#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 202#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 203#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 204 205#define CONFIG_ENV_IS_IN_FLASH 1 206#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ 207#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ 208#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ 209 210/* Address and size of Redundant Environment Sector */ 211#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) 212#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 213 214/*----------------------------------------------------------------------- 215 * Hardware Information Block 216 */ 217#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 218#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 219#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 220 221/*----------------------------------------------------------------------- 222 * Cache Configuration 223 */ 224#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 225#if defined(CONFIG_CMD_KGDB) 226#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 227#endif 228 229/*----------------------------------------------------------------------- 230 * SYPCR - System Protection Control 11-9 231 * SYPCR can only be written once after reset! 232 *----------------------------------------------------------------------- 233 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 234 */ 235#if defined(CONFIG_WATCHDOG) 236#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 237 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 238#else 239#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 240#endif 241 242/*----------------------------------------------------------------------- 243 * SIUMCR - SIU Module Configuration 11-6 244 *----------------------------------------------------------------------- 245 * PCMCIA config., multi-function pin tri-state 246 */ 247#ifndef CONFIG_CAN_DRIVER 248#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 249#else /* we must activate GPL5 in the SIUMCR for CAN */ 250#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 251#endif /* CONFIG_CAN_DRIVER */ 252 253/*----------------------------------------------------------------------- 254 * TBSCR - Time Base Status and Control 11-26 255 *----------------------------------------------------------------------- 256 * Clear Reference Interrupt Status, Timebase freezing enabled 257 */ 258#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 259 260/*----------------------------------------------------------------------- 261 * PISCR - Periodic Interrupt Status and Control 11-31 262 *----------------------------------------------------------------------- 263 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 264 */ 265#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 266 267/*----------------------------------------------------------------------- 268 * SCCR - System Clock and reset Control Register 15-27 269 *----------------------------------------------------------------------- 270 * Set clock output, timebase and RTC source and divider, 271 * power management and some other internal clocks 272 */ 273#define SCCR_MASK SCCR_EBDF11 274#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 275 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 276 SCCR_DFALCD00) 277 278/*----------------------------------------------------------------------- 279 * PCMCIA stuff 280 *----------------------------------------------------------------------- 281 * 282 */ 283#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 284#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 285#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 286#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 287#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 288#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 289#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 290#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 291 292/*----------------------------------------------------------------------- 293 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 294 *----------------------------------------------------------------------- 295 */ 296 297#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ 298#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 299 300#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 301#undef CONFIG_IDE_LED /* LED for ide not supported */ 302#undef CONFIG_IDE_RESET /* reset for ide not supported */ 303 304#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 305#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 306 307#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 308 309#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 310 311/* Offset for data I/O */ 312#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 313 314/* Offset for normal register accesses */ 315#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 316 317/* Offset for alternate registers */ 318#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 319 320/*----------------------------------------------------------------------- 321 * 322 *----------------------------------------------------------------------- 323 * 324 */ 325#define CONFIG_SYS_DER 0 326 327/* 328 * Init Memory Controller: 329 * 330 * BR0/1 and OR0/1 (FLASH) 331 */ 332 333#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 334#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 335 336/* used to re-map FLASH both when starting from SRAM or FLASH: 337 * restrict access enough to keep SRAM working (if any) 338 * but not too much to meddle with FLASH accesses 339 */ 340#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 341#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 342 343/* 344 * FLASH timing: Default value of OR0 after reset 345 */ 346#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ 347 OR_SCY_6_CLK | OR_TRLX) 348 349#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 350#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 351#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 352 353#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 354#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 355#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 356 357/* 358 * BR2/3 and OR2/3 (SDRAM) 359 * 360 */ 361#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 362#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 363#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */ 364 365/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 366#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 367 368#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 369#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 370 371#ifndef CONFIG_CAN_DRIVER 372#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 373#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 374#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 375#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 376#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 377#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 378#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 379 BR_PS_8 | BR_MS_UPMB | BR_V ) 380#endif /* CONFIG_CAN_DRIVER */ 381 382/* 383 * 4096 Rows from SDRAM example configuration 384 * 1000 factor s -> ms 385 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration 386 * 4 Number of refresh cycles per period 387 * 64 Refresh cycle in ms per number of rows 388 */ 389#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) 390 391/* 392 * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad) 393 * 394 * CPUclock(MHz) * 31.2 395 * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0 396 * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16 397 * 398 * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us 399 * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us 400 * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us 401 * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us 402 * 403 * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will 404 * be met also in the default configuration, i.e. if environment variable 405 * 'cpuclk' is not set. 406 */ 407#define CONFIG_SYS_MAMR_PTA 128 408 409/* 410 * Memory Periodic Timer Prescaler Register (MPTPR) values. 411 */ 412/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */ 413#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 414/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */ 415#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 416 417/* 418 * MAMR settings for SDRAM 419 */ 420 421/* 8 column SDRAM */ 422#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 423 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 424 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 425/* 9 column SDRAM */ 426#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 427 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 428 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 429/* 10 column SDRAM */ 430#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 431 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ 432 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 433 434/* 435 * Network configuration 436 */ 437#define CONFIG_SCC2_ENET /* enable ethernet on SCC2 */ 438#define CONFIG_FEC_ENET /* enable ethernet on FEC */ 439#define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */ 440#define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */ 441 442#if defined(CONFIG_CMD_MII) 443#define CONFIG_SYS_DISCOVER_PHY 444#define CONFIG_MII_INIT 1 445#endif 446 447#define CONFIG_NET_RETRY_COUNT 1 /* reduce max. timeout before 448 switching to another netwok (if the 449 tried network is unreachable) */ 450 451#define CONFIG_ETHPRIME "SCC" 452 453#define CONFIG_HWCONFIG 1 454 455#endif /* __CONFIG_H */ 456