LXR uboot/include/configs/VOM405.h

   1/*
   2 * (C) Copyright 2001-2004
   3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8/*
   9 * board/config.h - configuration options, board specific
  10 */
  11#ifndef __CONFIG_H
  12#define __CONFIG_H
  13
  14/*
  15 * High Level Configuration Options
  16 * (easy to change)
  17 */
  18#define CONFIG_405EP            1       /* This is a PPC405 CPU         */
  19#define CONFIG_VOM405           1       /* ...on a VOM405 board         */
  20
  21#define CONFIG_SYS_TEXT_BASE    0xFFFC8000
  22
  23#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  24
  25#define CONFIG_SYS_CLK_FREQ     33330000 /* external frequency to pll   */
  26
  27#define CONFIG_BAUDRATE         9600
  28
  29#undef  CONFIG_BOOTARGS
  30#undef  CONFIG_BOOTCOMMAND
  31
  32#define CONFIG_PREBOOT                  /* enable preboot variable      */
  33
  34#define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  35
  36#undef  CONFIG_HAS_ETH1
  37
  38#define CONFIG_PPC4xx_EMAC
  39#define CONFIG_MII              1       /* MII PHY management           */
  40#define CONFIG_PHY_ADDR         0       /* PHY address                  */
  41#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
  42#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
  43
  44/*
  45 * BOOTP options
  46 */
  47#define CONFIG_BOOTP_SUBNETMASK
  48#define CONFIG_BOOTP_GATEWAY
  49#define CONFIG_BOOTP_HOSTNAME
  50#define CONFIG_BOOTP_BOOTPATH
  51#define CONFIG_BOOTP_DNS
  52#define CONFIG_BOOTP_DNS2
  53#define CONFIG_BOOTP_SEND_HOSTNAME
  54
  55/*
  56 * Command line configuration.
  57 */
  58#define CONFIG_CMD_BSP
  59#define CONFIG_CMD_IRQ
  60#define CONFIG_CMD_EEPROM
  61
  62#undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  63
  64#define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
  65
  66#undef  CONFIG_PRAM                     /* no "protected RAM"           */
  67
  68/*
  69 * Miscellaneous configurable options
  70 */
  71#define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  72
  73#if defined(CONFIG_CMD_KGDB)
  74#define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
  75#else
  76#define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
  77#endif
  78#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  79#define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
  80#define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  81
  82#define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device       */
  83
  84#define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
  85#define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
  86
  87#define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  88#define CONFIG_SYS_NS16550_SERIAL
  89#define CONFIG_SYS_NS16550_REG_SIZE     1
  90#define CONFIG_SYS_NS16550_CLK          get_serial_clock()
  91
  92#undef  CONFIG_SYS_EXT_SERIAL_CLOCK            /* no external serial clock used */
  93#define CONFIG_SYS_BASE_BAUD        691200
  94
  95/* The following table includes the supported baudrates */
  96#define CONFIG_SYS_BAUDRATE_TABLE       \
  97        { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
  98         57600, 115200, 230400, 460800, 921600 }
  99
 100#define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 101#define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 102
 103#define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 104
 105#define CONFIG_SYS_RX_ETH_BUFFER        16      /* use 16 rx buffer on 405 emac */
 106
 107/*
 108 * For booting Linux, the board info and command line data
 109 * have to be in the first 8 MB of memory, since this is
 110 * the maximum mapped by the Linux kernel during initialization.
 111 */
 112#define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 113/*
 114 * FLASH organization
 115 */
 116#define FLASH_BASE0_PRELIM      0xFFC00000      /* FLASH bank #0        */
 117
 118#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 119#define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 120
 121#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 122#define CONFIG_SYS_FLASH_WRITE_TOUT     1000    /* Timeout for Flash Write (in ms)      */
 123
 124#define CONFIG_SYS_FLASH_WORD_SIZE      unsigned short  /* flash word size (width)      */
 125#define CONFIG_SYS_FLASH_ADDR0          0x5555  /* 1st address for flash config cycles  */
 126#define CONFIG_SYS_FLASH_ADDR1          0x2AAA  /* 2nd address for flash config cycles  */
 127/*
 128 * The following defines are added for buggy IOP480 byte interface.
 129 * All other boards should use the standard values (CPCI405 etc.)
 130 */
 131#define CONFIG_SYS_FLASH_READ0          0x0000  /* 0 is standard                        */
 132#define CONFIG_SYS_FLASH_READ1          0x0001  /* 1 is standard                        */
 133#define CONFIG_SYS_FLASH_READ2          0x0002  /* 2 is standard                        */
 134
 135#define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 136
 137/*
 138 * Start addresses for the final memory configuration
 139 * (Set up by the startup code)
 140 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 141 */
 142#define CONFIG_SYS_SDRAM_BASE           0x00000000
 143#define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_MONITOR_BASE
 144#define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 145#define CONFIG_SYS_MONITOR_LEN          (~(CONFIG_SYS_TEXT_BASE) + 1)
 146#define CONFIG_SYS_MALLOC_LEN           (256 * 1024)
 147
 148#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
 149# define CONFIG_SYS_RAMBOOT             1
 150#else
 151# undef CONFIG_SYS_RAMBOOT
 152#endif
 153
 154/*
 155 * Environment Variable setup
 156 */
 157#define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 158#define CONFIG_ENV_OFFSET               0x100   /* environment starts at the beginning of the EEPROM */
 159#define CONFIG_ENV_SIZE         0x700   /* 2048 bytes may be used for env vars*/
 160                                   /* total size of a CAT24WC16 is 2048 bytes */
 161
 162#define CONFIG_SYS_NVRAM_BASE_ADDR      0xF0000500              /* NVRAM base address   */
 163#define CONFIG_SYS_NVRAM_SIZE           242                     /* NVRAM size           */
 164
 165/*
 166 * I2C EEPROM (CAT24WC16) for environment
 167 */
 168#define CONFIG_SYS_I2C
 169#define CONFIG_SYS_I2C_PPC4XX
 170#define CONFIG_SYS_I2C_PPC4XX_CH0
 171#define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 172#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 173
 174#define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT28WC08             */
 175#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address             */
 176/* mask of address bits that overflow into the "EEPROM chip address"    */
 177#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 178#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24WC08 has   */
 179                                        /* 16 byte page write mode using*/
 180                                        /* last 4 bits of the address   */
 181#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
 182
 183/*
 184 * External Bus Controller (EBC) Setup
 185 */
 186#define CAN_BA          0xF0000000          /* CAN Base Address                 */
 187
 188/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
 189#define CONFIG_SYS_EBC_PB0AP            0x92015480
 190#define CONFIG_SYS_EBC_PB0CR            0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 191
 192/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization              */
 193#define CONFIG_SYS_EBC_PB2AP            0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 194#define CONFIG_SYS_EBC_PB2CR            0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 195
 196/*
 197 * FPGA stuff
 198 */
 199#define CONFIG_SYS_XSVF_DEFAULT_ADDR    0xfffc0000
 200
 201/* FPGA program pin configuration */
 202#define CONFIG_SYS_FPGA_PRG             0x04000000  /* JTAG TMS pin (ppc output)     */
 203#define CONFIG_SYS_FPGA_CLK             0x02000000  /* JTAG TCK pin (ppc output)     */
 204#define CONFIG_SYS_FPGA_DATA            0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
 205#define CONFIG_SYS_FPGA_INIT            0x00010000  /* unused (ppc input)            */
 206#define CONFIG_SYS_FPGA_DONE            0x00008000  /* JTAG TDI->TDO pin (ppc input) */
 207
 208/*
 209 * Definitions for initial stack pointer and data area (in data cache)
 210 */
 211/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 212#define CONFIG_SYS_TEMP_STACK_OCM         1
 213
 214/* On Chip Memory location */
 215#define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 216#define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 217#define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM             */
 218#define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM    */
 219
 220#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 221#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 222
 223/*
 224 * Definitions for GPIO setup (PPC405EP specific)
 225 *
 226 * GPIO0[0]     - External Bus Controller BLAST output
 227 * GPIO0[1-9]   - Instruction trace outputs -> GPIO
 228 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 229 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
 230 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 231 * GPIO0[24-27] - UART0 control signal inputs/outputs
 232 * GPIO0[28-29] - UART1 data signal input/output
 233 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
 234 */
 235/* GPIO Input:          OSR=00, ISR=00, TSR=00, TCR=0 */
 236/* GPIO Output:         OSR=00, ISR=00, TSR=00, TCR=1 */
 237/* Alt. Funtion Input:  OSR=00, ISR=01, TSR=00, TCR=0 */
 238/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
 239#define CONFIG_SYS_GPIO0_OSRL           0x40000500  /*  0 ... 15 */
 240#define CONFIG_SYS_GPIO0_OSRH           0x00000110  /* 16 ... 31 */
 241#define CONFIG_SYS_GPIO0_ISR1L          0x00000000  /*  0 ... 15 */
 242#define CONFIG_SYS_GPIO0_ISR1H          0x14000045  /* 16 ... 31 */
 243#define CONFIG_SYS_GPIO0_TSRL           0x00000000  /*  0 ... 15 */
 244#define CONFIG_SYS_GPIO0_TSRH           0x00000000  /* 16 ... 31 */
 245#define CONFIG_SYS_GPIO0_TCR            0xF7FE0014  /*  0 ... 31 */
 246
 247/*
 248 * Default speed selection (cpu_plb_opb_ebc) in mhz.
 249 * This value will be set if iic boot eprom is disabled.
 250 */
 251#define PLLMR0_DEFAULT   PLLMR0_133_66_66_33
 252#define PLLMR1_DEFAULT   PLLMR1_133_66_66_33
 253
 254#endif  /* __CONFIG_H */
 255