LXR uboot/include/configs/digsy

   1/*
   2 * (C) Copyright 2003-2004
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * (C) Copyright 2005-2007
   6 * Modified for InterControl digsyMTC MPC5200 board by
   7 * Frank Bodammer, GCD Hard- & Software GmbH,
   8 *                 frank.bodammer@gcd-solutions.de
   9 *
  10 * (C) Copyright 2009 Semihalf
  11 * Optimized for digsyMTC by: Grzegorz Bernacki <gjb@semihalf.com>
  12 *
  13 * SPDX-License-Identifier:     GPL-2.0+
  14 */
  15
  16#ifndef __CONFIG_H
  17#define __CONFIG_H
  18
  19/*
  20 * High Level Configuration Options
  21 */
  22
  23#define CONFIG_MPC5200          1       /* This is an MPC5200 CPU */
  24#define CONFIG_DIGSY_MTC        1       /* ... on InterControl digsyMTC board */
  25
  26/*
  27 * Valid values for CONFIG_SYS_TEXT_BASE are:
  28 * 0xFFF00000   boot high (standard configuration)
  29 * 0xFE000000   boot low
  30 * 0x00100000   boot from RAM (for testing only)
  31 */
  32#ifndef CONFIG_SYS_TEXT_BASE
  33#define CONFIG_SYS_TEXT_BASE    0xFFF00000      /* Standard: boot high */
  34#endif
  35
  36#define CONFIG_SYS_MPC5XXX_CLKIN        33000000
  37
  38#define CONFIG_SYS_CACHELINE_SIZE       32
  39
  40/*
  41 * Serial console configuration
  42 */
  43#define CONFIG_PSC_CONSOLE      4       /* console is on PSC4  */
  44#define CONFIG_BAUDRATE         115200  /* ... at 115200  bps  */
  45#define CONFIG_SYS_BAUDRATE_TABLE       \
  46        { 9600, 19200, 38400, 57600, 115200, 230400 }
  47
  48/*
  49 * PCI Mapping:
  50 * 0x40000000 - 0x4fffffff - PCI Memory
  51 * 0x50000000 - 0x50ffffff - PCI IO Space
  52 */
  53#define CONFIG_PCI_SCAN_SHOW    1
  54#define CONFIG_PCI_BOOTDELAY    250
  55
  56#define CONFIG_PCI_MEM_BUS      0x40000000
  57#define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  58#define CONFIG_PCI_MEM_SIZE     0x10000000
  59
  60#define CONFIG_PCI_IO_BUS       0x50000000
  61#define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  62#define CONFIG_PCI_IO_SIZE      0x01000000
  63
  64#define CONFIG_BZIP2
  65
  66/*
  67 * Video
  68 */
  69
  70#ifdef CONFIG_VIDEO
  71#define CONFIG_VIDEO_MB862xx
  72#define CONFIG_VIDEO_MB862xx_ACCEL
  73#define CONFIG_VIDEO_CORALP
  74#define CONFIG_VIDEO_LOGO
  75#define CONFIG_VIDEO_BMP_LOGO
  76#define CONFIG_SPLASH_SCREEN
  77#define CONFIG_VIDEO_BMP_GZIP
  78#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  (2 << 20)       /* decompressed img */
  79
  80/* Coral-PA clock frequency, geo and other both 133MHz */
  81#define CONFIG_SYS_MB862xx_CCF  0x00050000
  82/* Video SDRAM parameters */
  83#define CONFIG_SYS_MB862xx_MMR  0x11d7fa72
  84#endif
  85
  86/*
  87 * Command line configuration.
  88 */
  89#ifdef CONFIG_VIDEO
  90#define CONFIG_CMD_BMP
  91#endif
  92#define CONFIG_CMD_DATE
  93#define CONFIG_CMD_DIAG
  94#define CONFIG_CMD_EEPROM
  95#define CONFIG_CMD_IDE
  96#define CONFIG_CMD_IRQ
  97#define CONFIG_CMD_PCI
  98#define CONFIG_CMD_REGINFO
  99#define CONFIG_CMD_SAVES
 100
 101#if (CONFIG_SYS_TEXT_BASE == 0xFF000000)
 102#define CONFIG_SYS_LOWBOOT      1
 103#endif
 104
 105/*
 106 * Autobooting
 107 */
 108
 109#undef  CONFIG_BOOTARGS
 110
 111#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 112        "fw_image=digsyMPC.img\0"                                       \
 113        "mtcb_start=mtc led diag orange; run mtcb_1\0"                  \
 114        "mtcb_clearled=for x in user1 user2 usbpwr usbbusy; "           \
 115                "do mtc led $x; done\0"                                 \
 116        "mtcb_1=if mtc key; then run mtcb_clearled mtcb_update; "       \
 117                "else run mtcb_fw; fi\0"                                \
 118        "mtcb_fw=if bootm ff000000; then echo FIRMWARE OK!; "           \
 119                "else echo BAD FIRMWARE CRC!; mtc led diag red; fi\0"   \
 120        "mtcb_update=mtc led user1 orange;"                             \
 121                "while mtc key; do ; done; run mtcb_2;\0"               \
 122        "mtcb_2=mtc led user1 green 2; usb reset; run mtcb_usb1;\0"     \
 123        "mtcb_usb1=if fatload usb 0 400000 script.img; "                \
 124                "then run mtcb_doscript; else run mtcb_usb2; fi\0"      \
 125        "mtcb_usb2=if fatload usb 0 400000 $fw_image; "                 \
 126                "then run mtcb_dousb; else run mtcb_ide; fi\0"          \
 127        "mtcb_doscript=run mtcb_usbleds; mtc led user2 orange 2; "      \
 128                "run mtcb_wait_flickr mtcb_ds_1;\0"                     \
 129        "mtcb_ds_1=if imi 400000; then mtc led usbbusy; "               \
 130                "source 400000; else run mtcb_error; fi\0"              \
 131        "mtcb_dousb=run mtcb_usbleds mtcb_wait_flickr mtcb_du_1;\0"     \
 132        "mtcb_du_1=if imi 400000; then run mtcb_du_2; "                 \
 133                "else run mtcb_error; fi\0"                             \
 134        "mtcb_du_2=run mtcb_clear mtcb_prog; mtc led usbbusy; "         \
 135                "run mtcb_checkfw\0"                                    \
 136        "mtcb_checkfw=if imi ff000000; then run mtcb_success; "         \
 137                "else run mtcb_error; fi\0"                             \
 138        "mtcb_waitkey=mtc key; until test $? -eq 0; do mtc key; done\0" \
 139        "mtcb_wait_flickr=run mtcb_waitkey mtcb_uledflckr\0"            \
 140        "mtcb_usbleds=mtc led usbpwr green; mtc led usbbusy orange 1;\0"\
 141        "mtcb_uledflckr=mtc led user1 orange 11\0"                      \
 142        "mtcb_error=mtc led user1 red\0"                                \
 143        "mtcb_clear=erase ff000000 ff0fffff\0"                          \
 144        "mtcb_prog=cp.b 400000 ff000000 ${filesize}\0"                  \
 145        "mtcb_success=mtc led user1 green\0"                            \
 146        "mtcb_ide=if fatload ide 0 400000 $fw_image;"                   \
 147                "then run mtcb_doide; else run mtcb_error; fi\0"        \
 148        "mtcb_doide=mtc led user2 green 1;"                             \
 149                "run mtcb_wait_flickr mtcb_di_1;\0"                     \
 150        "mtcb_di_1=if imi 400000; then run mtcb_di_2;"                  \
 151                "else run mtcb_error; fi\0"                             \
 152        "mtcb_di_2=run mtcb_clear; run mtcb_prog mtcb_checkfw\0"        \
 153        "ramdisk_num_sector=16\0"                                       \
 154        "flash_base=ff000000\0"                                         \
 155        "flashdisk_size=e00000\0"                                       \
 156        "env_sector=fff60000\0"                                         \
 157        "flashdisk_start=ff100000\0"                                    \
 158        "load_cmd=tftp 400000 digsyMPC.img\0"                           \
 159        "clear_cmd=erase ff000000 ff0fffff\0"                           \
 160        "flash_cmd=cp.b 400000 ff000000 ${filesize}\0"                  \
 161        "update_cmd=run load_cmd; "                                     \
 162        "iminfo 400000; "                                               \
 163        "run clear_cmd flash_cmd; "                                     \
 164        "iminfo ff000000\0"                                             \
 165        "spi_driver=yes\0"                                              \
 166        "spi_watchdog=no\0"                                             \
 167        "ftps_start=yes\0"                                              \
 168        "ftps_user1=admin\0"                                            \
 169        "ftps_pass1=admin\0"                                            \
 170        "ftps_base1=/\0"                                                \
 171        "ftps_home1=/\0"                                                \
 172        "plc_sio_srv=no\0"                                              \
 173        "plc_sio_baud=57600\0"                                          \
 174        "plc_sio_parity=no\0"                                           \
 175        "plc_sio_stop=1\0"                                              \
 176        "plc_sio_com=2\0"                                               \
 177        "plc_eth_srv=yes\0"                                             \
 178        "plc_eth_port=1200\0"                                           \
 179        "plc_root=/ide/\0"                                              \
 180        "diag_level=0\0"                                                \
 181        "webvisu=no\0"                                                  \
 182        "plc_can1_routing=no\0"                                         \
 183        "plc_can1_baudrate=250\0"                                       \
 184        "plc_can2_routing=no\0"                                         \
 185        "plc_can2_baudrate=250\0"                                       \
 186        "plc_can3_routing=no\0"                                         \
 187        "plc_can3_baudrate=250\0"                                       \
 188        "plc_can4_routing=no\0"                                         \
 189        "plc_can4_baudrate=250\0"                                       \
 190        "netdev=eth0\0"                                                 \
 191        "console=ttyPSC0\0"                                             \
 192        "kernel_addr_r=400000\0"                                        \
 193        "fdt_addr_r=600000\0"                                           \
 194        "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 195        "nfsroot=${serverip}:${rootpath}\0"                             \
 196        "addip=setenv bootargs ${bootargs} "                            \
 197        "ip=${ipaddr}:${serverip}:${gatewayip}:"                        \
 198        "${netmask}:${hostname}:${netdev}:off panic=1\0"                \
 199        "addcons=setenv bootargs ${bootargs} console=${console},${baudrate}\0"\
 200        "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 201        "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
 202                "tftp ${fdt_addr_r} ${fdt_file};"                       \
 203                "run nfsargs addip addcons;"                            \
 204                "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 205        "load=tftp 200000 ${u-boot}\0"                                  \
 206        "update=protect off FFF00000 +${filesize};"                     \
 207                "erase FFF00000 +${filesize};"                          \
 208                "cp.b 200000 FFF00000 ${filesize};"                     \
 209                "protect on FFF00000 +${filesize}\0"                    \
 210        ""
 211
 212#define CONFIG_BOOTCOMMAND      "run mtcb_start"
 213
 214/*
 215 * I2C configuration
 216 */
 217#define CONFIG_HARD_I2C         1
 218#define CONFIG_SYS_I2C_MODULE   1
 219#define CONFIG_SYS_I2C_SPEED    100000
 220#define CONFIG_SYS_I2C_SLAVE    0x7F
 221
 222/*
 223 * EEPROM configuration
 224 */
 225#define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* 1010000x */
 226#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 227#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 228#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   70
 229
 230/*
 231 * RTC configuration
 232 */
 233#if defined(CONFIG_DIGSY_REV5)
 234#define CONFIG_SYS_I2C_RTC_ADDR 0x56
 235#define CONFIG_RTC_RV3029
 236/* Enable 5k Ohm trickle charge resistor */
 237#define CONFIG_SYS_RV3029_TCR   0x20
 238#else
 239#define CONFIG_RTC_DS1337
 240#define CONFIG_SYS_I2C_RTC_ADDR 0x68
 241#define CONFIG_SYS_DS1339_TCR_VAL       0xAB    /* diode + 4k resistor */
 242#endif
 243
 244/*
 245 * Flash configuration
 246 */
 247#define CONFIG_SYS_FLASH_CFI            1
 248#define CONFIG_FLASH_CFI_DRIVER 1
 249
 250#if defined(CONFIG_DIGSY_REV5)
 251#define CONFIG_SYS_FLASH_BASE           0xFE000000
 252#define CONFIG_SYS_FLASH_BASE_CS1       0xFC000000
 253#define CONFIG_SYS_MAX_FLASH_BANKS      2
 254#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE, \
 255                                        CONFIG_SYS_FLASH_BASE_CS1}
 256#define CONFIG_SYS_UPDATE_FLASH_SIZE
 257#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
 258#else
 259#define CONFIG_SYS_FLASH_BASE           0xFF000000
 260#define CONFIG_SYS_MAX_FLASH_BANKS      1
 261#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 262#endif
 263
 264#define CONFIG_SYS_MAX_FLASH_SECT       256
 265#define CONFIG_FLASH_16BIT
 266#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
 267#define CONFIG_SYS_FLASH_SIZE   0x01000000
 268#define CONFIG_SYS_FLASH_ERASE_TOUT     240000
 269#define CONFIG_SYS_FLASH_WRITE_TOUT     500
 270
 271#define OF_CPU                  "PowerPC,5200@0"
 272#define OF_SOC                  "soc5200@f0000000"
 273#define OF_TBCLK                (bd->bi_busfreq / 4)
 274
 275#define CONFIG_BOARD_EARLY_INIT_R
 276#define CONFIG_MISC_INIT_R
 277
 278/*
 279 * Environment settings
 280 */
 281#define CONFIG_ENV_IS_IN_FLASH  1
 282#if defined(CONFIG_LOWBOOT)
 283#define CONFIG_ENV_ADDR         0xFF060000
 284#else   /* CONFIG_LOWBOOT */
 285#define CONFIG_ENV_ADDR         0xFFF60000
 286#endif  /* CONFIG_LOWBOOT */
 287#define CONFIG_ENV_SIZE         0x10000
 288#define CONFIG_ENV_SECT_SIZE    0x20000
 289#define CONFIG_ENV_OVERWRITE    1
 290
 291/*
 292 * Memory map
 293 */
 294#define CONFIG_SYS_MBAR         0xF0000000
 295#define CONFIG_SYS_SDRAM_BASE           0x00000000
 296#if !defined(CONFIG_SYS_LOWBOOT)
 297#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 298#else
 299#define CONFIG_SYS_DEFAULT_MBAR 0xF0000000
 300#endif
 301
 302/*
 303 *  Use SRAM until RAM will be available
 304 */
 305#define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 306#define CONFIG_SYS_INIT_RAM_SIZE                MPC5XXX_SRAM_SIZE
 307
 308#define CONFIG_SYS_GBL_DATA_OFFSET      \
 309        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 310#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 311
 312#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 313#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 314#define CONFIG_SYS_RAMBOOT              1
 315#endif
 316
 317#define CONFIG_SYS_MONITOR_LEN  (256 << 10)
 318#define CONFIG_SYS_MALLOC_LEN   (4096 << 10)
 319#define CONFIG_SYS_BOOTMAPSZ    (8 << 20)
 320
 321/*
 322 * Ethernet configuration
 323 */
 324#define CONFIG_MPC5xxx_FEC      1
 325#define CONFIG_MPC5xxx_FEC_MII100
 326#if defined(CONFIG_DIGSY_REV5)
 327#define CONFIG_PHY_ADDR         0x01
 328#else
 329#define CONFIG_PHY_ADDR         0x00
 330#endif
 331#define CONFIG_PHY_RESET_DELAY  1000
 332
 333#define CONFIG_NETCONSOLE               /* include NetConsole support   */
 334
 335/*
 336 * GPIO configuration
 337 * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1)
 338 *  Bit 0   (mask 0x80000000) : 0x1
 339 * SPI on Tmr2/3/4/5 pins
 340 *  Bit 2:3 (mask 0x30000000) : 0x2
 341 * ATA cs0/1 on csb_4/5
 342 *  Bit 6:7 (mask 0x03000000) : 0x2
 343 * Ethernet 100Mbit with MD
 344 *  Bits 12:15 (mask 0x000f0000): 0x5
 345 * USB - Two UARTs
 346 *  Bits 18:19 (mask 0x00003000) : 0x2
 347 * PSC3 - USB2 on PSC3
 348 *  Bits 20:23 (mask 0x00000f00) : 0x1
 349 * PSC2 - CAN1&2 on PSC2 pins
 350 *  Bits 25:27 (mask 0x00000070) : 0x1
 351 * PSC1 - AC97 functionality
 352 *  Bits 29:31 (mask 0x00000007) : 0x2
 353 */
 354#define CONFIG_SYS_GPS_PORT_CONFIG      0xA2552112
 355
 356/*
 357 * Miscellaneous configurable options
 358 */
 359#define CONFIG_SYS_LONGHELP
 360#define CONFIG_AUTO_COMPLETE    1
 361#define CONFIG_CMDLINE_EDITING  1
 362
 363#define CONFIG_MX_CYCLIC        1
 364
 365#define CONFIG_SYS_CBSIZE               1024
 366#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 367#define CONFIG_SYS_MAXARGS              32
 368#define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 369
 370#define CONFIG_SYS_ALT_MEMTEST
 371#define CONFIG_SYS_MEMTEST_SCRATCH      0x00001000
 372#define CONFIG_SYS_MEMTEST_START        0x00010000
 373#define CONFIG_SYS_MEMTEST_END          0x019fffff
 374
 375#define CONFIG_SYS_LOAD_ADDR            0x00100000
 376
 377/*
 378 * Various low-level settings
 379 */
 380#define CONFIG_SYS_SDRAM_CS1            1
 381#define CONFIG_SYS_XLB_PIPELINING       1
 382
 383#define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 384#define CONFIG_SYS_HID0_FINAL           HID0_ICE
 385
 386#if defined(CONFIG_SYS_LOWBOOT)
 387#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 388#define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 389#define CONFIG_SYS_BOOTCS_CFG           0x0002DD00
 390#endif
 391
 392#define CONFIG_SYS_CS4_START            0x60000000
 393#define CONFIG_SYS_CS4_SIZE             0x1000
 394#define CONFIG_SYS_CS4_CFG              0x0008FC00
 395
 396#define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 397#define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 398#define CONFIG_SYS_CS0_CFG              0x0002DD00
 399
 400#if defined(CONFIG_DIGSY_REV5)
 401#define CONFIG_SYS_CS1_START            CONFIG_SYS_FLASH_BASE_CS1
 402#define CONFIG_SYS_CS1_SIZE             CONFIG_SYS_FLASH_SIZE
 403#define CONFIG_SYS_CS1_CFG              0x0002DD00
 404#endif
 405
 406#define CONFIG_SYS_CS_BURST             0x00000000
 407#define CONFIG_SYS_CS_DEADCYCLE 0x11111111
 408
 409#if !defined(CONFIG_SYS_LOWBOOT)
 410#define CONFIG_SYS_RESET_ADDRESS        0xfff00100
 411#else
 412#define CONFIG_SYS_RESET_ADDRESS        0xff000100
 413#endif
 414
 415/*
 416 * USB
 417 */
 418#define CONFIG_USB_OHCI_NEW
 419#define CONFIG_SYS_OHCI_BE_CONTROLLER
 420
 421#define CONFIG_USB_CLOCK        0x00013333
 422#define CONFIG_USB_CONFIG       0x00002000
 423
 424#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 425#define CONFIG_SYS_USB_OHCI_REGS_BASE   MPC5XXX_USB
 426#define CONFIG_SYS_USB_OHCI_SLOT_NAME   "mpc5200"
 427#define CONFIG_SYS_USB_OHCI_CPU_INIT
 428
 429/*
 430 * IDE/ATA
 431 */
 432#define CONFIG_IDE_RESET
 433#define CONFIG_IDE_PREINIT
 434
 435#define CONFIG_SYS_ATA_CS_ON_I2C2
 436#define CONFIG_SYS_IDE_MAXBUS           1
 437#define CONFIG_SYS_IDE_MAXDEVICE        1
 438
 439#define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 440#define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 441#define CONFIG_SYS_ATA_DATA_OFFSET      (0x0060)
 442#define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 443#define CONFIG_SYS_ATA_ALT_OFFSET       (0x005C)
 444#define CONFIG_SYS_ATA_STRIDE           4
 445
 446#define CONFIG_ATAPI            1
 447#define CONFIG_LBA48            1
 448
 449#endif /* __CONFIG_H */
 450