LXR uboot/include/configs/dlvision-10g.h

   1/*
   2 * (C) Copyright 2010
   3 * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8#ifndef __CONFIG_H
   9#define __CONFIG_H
  10
  11#define CONFIG_405EP            1       /* this is a PPC405 CPU */
  12#define CONFIG_DLVISION_10G     1       /*  on a DLVision-10G board */
  13
  14#define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  15
  16/*
  17 * Include common defines/options for all AMCC eval boards
  18 */
  19#define CONFIG_HOSTNAME         dlvsion-10g
  20#include "amcc-common.h"
  21
  22#define CONFIG_BOARD_EARLY_INIT_R
  23#define CONFIG_MISC_INIT_R
  24#define CONFIG_LAST_STAGE_INIT
  25
  26#define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
  27
  28/*
  29 * Configure PLL
  30 */
  31#define PLLMR0_DEFAULT PLLMR0_266_133_66
  32#define PLLMR1_DEFAULT PLLMR1_266_133_66
  33
  34/* new uImage format support */
  35#define CONFIG_FIT_DISABLE_SHA256
  36
  37#define CONFIG_ENV_IS_IN_FLASH  /* use FLASH for environment vars */
  38
  39/*
  40 * Default environment variables
  41 */
  42#define CONFIG_EXTRA_ENV_SETTINGS                                       \
  43        CONFIG_AMCC_DEF_ENV                                             \
  44        CONFIG_AMCC_DEF_ENV_POWERPC                                     \
  45        CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
  46        "kernel_addr=fc000000\0"                                        \
  47        "fdt_addr=fc1e0000\0"                                           \
  48        "ramdisk_addr=fc200000\0"                                       \
  49        ""
  50
  51#define CONFIG_PHY_ADDR         4       /* PHY address                  */
  52#define CONFIG_HAS_ETH0
  53#define CONFIG_HAS_ETH1
  54#define CONFIG_PHY1_ADDR        0xc     /* EMAC1 PHY address            */
  55#define CONFIG_PHY_CLK_FREQ     EMAC_STACR_CLK_66MHZ
  56
  57/*
  58 * Commands additional to the ones defined in amcc-common.h
  59 */
  60#define CONFIG_CMD_DTT
  61#undef CONFIG_CMD_DIAG
  62#undef CONFIG_CMD_EEPROM
  63#undef CONFIG_CMD_IRQ
  64
  65/*
  66 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
  67 */
  68#define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0 */
  69
  70/* SDRAM timings used in datasheet */
  71#define CONFIG_SYS_SDRAM_CL             3       /* CAS latency */
  72#define CONFIG_SYS_SDRAM_tRP           20       /* PRECHARGE command period */
  73#define CONFIG_SYS_SDRAM_tRC           66       /* ACTIVE-to-ACTIVE period */
  74#define CONFIG_SYS_SDRAM_tRCD          20       /* ACTIVE-to-READ delay */
  75#define CONFIG_SYS_SDRAM_tRFC          66       /* Auto refresh period */
  76
  77/*
  78 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
  79 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
  80 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
  81 * The Linux BASE_BAUD define should match this configuration.
  82 *    baseBaud = cpuClock/(uartDivisor*16)
  83 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
  84 * set Linux BASE_BAUD to 403200.
  85 */
  86#define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  87#undef  CONFIG_SYS_EXT_SERIAL_CLOCK     /* external serial clock */
  88#undef  CONFIG_SYS_405_UART_ERRATA_59   /* 405GP/CR Rev. D silicon */
  89#define CONFIG_SYS_BASE_BAUD            691200
  90
  91/*
  92 * I2C stuff
  93 */
  94#define CONFIG_SYS_I2C_PPC4XX
  95#define CONFIG_SYS_I2C_PPC4XX_CH0
  96#define CONFIG_SYS_I2C_PPC4XX_SPEED_0           100000
  97#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
  98
  99#define CONFIG_SYS_I2C_IHS
 100#define CONFIG_SYS_I2C_IHS_DUAL
 101#define CONFIG_SYS_I2C_IHS_CH0
 102#define CONFIG_SYS_I2C_IHS_SPEED_0              50000
 103#define CONFIG_SYS_I2C_IHS_SLAVE_0              0x7F
 104#define CONFIG_SYS_I2C_IHS_SPEED_0_1            50000
 105#define CONFIG_SYS_I2C_IHS_SLAVE_0_1            0x7F
 106#define CONFIG_SYS_I2C_IHS_CH1
 107#define CONFIG_SYS_I2C_IHS_SPEED_1              50000
 108#define CONFIG_SYS_I2C_IHS_SLAVE_1              0x7F
 109#define CONFIG_SYS_I2C_IHS_SPEED_1_1            50000
 110#define CONFIG_SYS_I2C_IHS_SLAVE_1_1            0x7F
 111
 112#define CONFIG_SYS_SPD_BUS_NUM          4
 113
 114/* Temp sensor/hwmon/dtt */
 115#define CONFIG_SYS_DTT_BUS_NUM  4
 116#define CONFIG_DTT_LM63         1       /* National LM63        */
 117#define CONFIG_DTT_SENSORS      { 0x4c, 0x4e, 0x18 } /* Sensor addresses */
 118#define CONFIG_DTT_PWM_LOOKUPTABLE      \
 119                { { 46, 10 }, { 48, 14 }, { 50, 19 }, { 52, 23 },\
 120                  { 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } }
 121#define CONFIG_DTT_TACH_LIMIT   0xa10
 122
 123#define CONFIG_SYS_ICS8N3QV01_I2C       {1, 3}
 124#define CONFIG_SYS_SIL1178_I2C          {0, 2}
 125#define CONFIG_SYS_DP501_I2C            {0, 2}
 126
 127/* EBC peripherals */
 128
 129#define CONFIG_SYS_FLASH_BASE           0xFC000000
 130#define CONFIG_SYS_FPGA0_BASE           0x7f100000
 131#define CONFIG_SYS_FPGA1_BASE           0x7f200000
 132#define CONFIG_SYS_LATCH_BASE           0x7f300000
 133
 134#define CONFIG_SYS_FPGA_BASE(k) \
 135        (k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE)
 136
 137#define CONFIG_SYS_FPGA_DONE(k) \
 138        (k ? 0x2000 : 0x1000)
 139
 140#define CONFIG_SYS_FPGA_COUNT           2
 141
 142#define CONFIG_SYS_FPGA_PTR { \
 143        (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \
 144        (struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE }
 145
 146#define CONFIG_SYS_FPGA_COMMON
 147
 148#define CONFIG_SYS_LATCH0_RESET         0xffff
 149#define CONFIG_SYS_LATCH0_BOOT          0xffff
 150#define CONFIG_SYS_LATCH1_RESET         0xffbf
 151#define CONFIG_SYS_LATCH1_BOOT          0xffff
 152
 153#define CONFIG_SYS_FPGA_NO_RFL_HI
 154
 155/*
 156 * FLASH organization
 157 */
 158#define CONFIG_SYS_FLASH_CFI            /* The flash is CFI compatible  */
 159#define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 160
 161#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 162
 163#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks */
 164#define CONFIG_SYS_MAX_FLASH_SECT       512     /* max num of sectors per chip*/
 165
 166#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase/ms */
 167#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write/ms */
 168
 169#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buff'd writes */
 170
 171#define CONFIG_SYS_FLASH_EMPTY_INFO     /* 'E' for empty sector on flinfo */
 172#define CONFIG_SYS_FLASH_QUIET_TEST     1       /* no warn upon unknown flash */
 173
 174#ifdef CONFIG_ENV_IS_IN_FLASH
 175#define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector */
 176#define CONFIG_ENV_ADDR         ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 177#define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector */
 178
 179/* Address and size of Redundant Environment Sector     */
 180#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 181#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 182#endif
 183
 184/*
 185 * PPC405 GPIO Configuration
 186 */
 187#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO     Alternate1      */ \
 188{ \
 189/* GPIO Core 0 */ \
 190{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO0   PerBLast */ \
 191{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1   TS1E */ \
 192{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2   TS2E */ \
 193{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3   TS1O */ \
 194{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4   TS2O */ \
 195{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO5   TS3 */ \
 196{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO6   TS4 */ \
 197{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO7   TS5 */ \
 198{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8   TS6 */ \
 199{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO9   TrcClk */ \
 200{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10  PerCS1 */ \
 201{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11  PerCS2 */ \
 202{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12  PerCS3 */ \
 203{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO13  PerCS4 */ \
 204{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14  PerAddr03 */ \
 205{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15  PerAddr04 */ \
 206{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16  PerAddr05 */ \
 207{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17  IRQ0 */ \
 208{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18  IRQ1 */ \
 209{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19  IRQ2 */ \
 210{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO20  IRQ3 */ \
 211{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO21  IRQ4 */ \
 212{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO22  IRQ5 */ \
 213{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23  IRQ6 */ \
 214{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24  UART0_DCD */ \
 215{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25  UART0_DSR */ \
 216{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26  UART0_RI */ \
 217{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27  UART0_DTR */ \
 218{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28  UART1_Rx */ \
 219{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29  UART1_Tx */ \
 220{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30  RejectPkt0 */ \
 221{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31  RejectPkt1 */ \
 222} \
 223}
 224
 225/*
 226 * Definitions for initial stack pointer and data area (in data cache)
 227 */
 228/* use on chip memory (OCM) for temperary stack until sdram is tested */
 229#define CONFIG_SYS_TEMP_STACK_OCM       1
 230
 231/* On Chip Memory location */
 232#define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 233#define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 234#define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
 235#define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE
 236
 237#define CONFIG_SYS_GBL_DATA_OFFSET \
 238        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 239#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 240
 241/*
 242 * External Bus Controller (EBC) Setup
 243 */
 244
 245/* Memory Bank 0 (NOR-flash) */
 246#define CONFIG_SYS_EBC_PB0AP    (EBC_BXAP_BME_ENABLED           |       \
 247                                 EBC_BXAP_FWT_ENCODE(8)         |       \
 248                                 EBC_BXAP_BWT_ENCODE(7)         |       \
 249                                 EBC_BXAP_BCE_DISABLE           |       \
 250                                 EBC_BXAP_BCT_2TRANS            |       \
 251                                 EBC_BXAP_CSN_ENCODE(0)         |       \
 252                                 EBC_BXAP_OEN_ENCODE(2)         |       \
 253                                 EBC_BXAP_WBN_ENCODE(2)         |       \
 254                                 EBC_BXAP_WBF_ENCODE(2)         |       \
 255                                 EBC_BXAP_TH_ENCODE(4)          |       \
 256                                 EBC_BXAP_RE_DISABLED           |       \
 257                                 EBC_BXAP_SOR_NONDELAYED        |       \
 258                                 EBC_BXAP_BEM_WRITEONLY         |       \
 259                                 EBC_BXAP_PEN_DISABLED)
 260#define CONFIG_SYS_EBC_PB0CR    (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
 261                                 EBC_BXCR_BS_64MB               |       \
 262                                 EBC_BXCR_BU_RW                 |       \
 263                                 EBC_BXCR_BW_16BIT)
 264
 265/* Memory Bank 1 (FPGA0) */
 266#define CONFIG_SYS_EBC_PB1AP    (EBC_BXAP_BME_DISABLED          |       \
 267                                 EBC_BXAP_TWT_ENCODE(5)         |       \
 268                                 EBC_BXAP_BCE_DISABLE           |       \
 269                                 EBC_BXAP_BCT_2TRANS            |       \
 270                                 EBC_BXAP_CSN_ENCODE(0)         |       \
 271                                 EBC_BXAP_OEN_ENCODE(2)         |       \
 272                                 EBC_BXAP_WBN_ENCODE(1)         |       \
 273                                 EBC_BXAP_WBF_ENCODE(1)         |       \
 274                                 EBC_BXAP_TH_ENCODE(0)          |       \
 275                                 EBC_BXAP_RE_DISABLED           |       \
 276                                 EBC_BXAP_SOR_NONDELAYED        |       \
 277                                 EBC_BXAP_BEM_WRITEONLY         |       \
 278                                 EBC_BXAP_PEN_DISABLED)
 279#define CONFIG_SYS_EBC_PB1CR    (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \
 280                                 EBC_BXCR_BS_1MB                |       \
 281                                 EBC_BXCR_BU_RW                 |       \
 282                                 EBC_BXCR_BW_16BIT)
 283
 284/* Memory Bank 2 (FPGA1) */
 285#define CONFIG_SYS_EBC_PB2AP    (EBC_BXAP_BME_DISABLED          |       \
 286                                 EBC_BXAP_TWT_ENCODE(6)         |       \
 287                                 EBC_BXAP_BCE_DISABLE           |       \
 288                                 EBC_BXAP_BCT_2TRANS            |       \
 289                                 EBC_BXAP_CSN_ENCODE(0)         |       \
 290                                 EBC_BXAP_OEN_ENCODE(2)         |       \
 291                                 EBC_BXAP_WBN_ENCODE(1)         |       \
 292                                 EBC_BXAP_WBF_ENCODE(1)         |       \
 293                                 EBC_BXAP_TH_ENCODE(0)          |       \
 294                                 EBC_BXAP_RE_DISABLED           |       \
 295                                 EBC_BXAP_SOR_NONDELAYED        |       \
 296                                 EBC_BXAP_BEM_WRITEONLY         |       \
 297                                 EBC_BXAP_PEN_DISABLED)
 298#define CONFIG_SYS_EBC_PB2CR    (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \
 299                                 EBC_BXCR_BS_1MB                |       \
 300                                 EBC_BXCR_BU_RW                 |       \
 301                                 EBC_BXCR_BW_16BIT)
 302
 303/* Memory Bank 3 (Latches) */
 304#define CONFIG_SYS_EBC_PB3AP    (EBC_BXAP_BME_ENABLED           |       \
 305                                 EBC_BXAP_FWT_ENCODE(8)         |       \
 306                                 EBC_BXAP_BWT_ENCODE(4)         |       \
 307                                 EBC_BXAP_BCE_DISABLE           |       \
 308                                 EBC_BXAP_BCT_2TRANS            |       \
 309                                 EBC_BXAP_CSN_ENCODE(0)         |       \
 310                                 EBC_BXAP_OEN_ENCODE(1)         |       \
 311                                 EBC_BXAP_WBN_ENCODE(1)         |       \
 312                                 EBC_BXAP_WBF_ENCODE(1)         |       \
 313                                 EBC_BXAP_TH_ENCODE(2)          |       \
 314                                 EBC_BXAP_RE_DISABLED           |       \
 315                                 EBC_BXAP_SOR_NONDELAYED        |       \
 316                                 EBC_BXAP_BEM_WRITEONLY         |       \
 317                                 EBC_BXAP_PEN_DISABLED)
 318#define CONFIG_SYS_EBC_PB3CR    (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \
 319                                 EBC_BXCR_BS_1MB                |       \
 320                                 EBC_BXCR_BU_RW                 |       \
 321                                 EBC_BXCR_BW_16BIT)
 322
 323/*
 324 * OSD Setup
 325 */
 326#define CONFIG_SYS_MPC92469AC
 327#define CONFIG_SYS_OSD_SCREENS          CONFIG_SYS_FPGA_COUNT
 328#define CONFIG_SYS_DP501_DIFFERENTIAL
 329#define CONFIG_SYS_DP501_VCAPCTRL0      0x01 /* DDR mode 0, DE for H/VSYNC */
 330
 331#endif  /* __CONFIG_H */
 332