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8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12
13
14
15#define CONFIG_E300 1
16#define CONFIG_MPC83xx 1
17#define CONFIG_MPC830x 1
18#define CONFIG_MPC8308 1
19#define CONFIG_HRCON 1
20
21#define CONFIG_SYS_TEXT_BASE 0xFE000000
22
23#define CONFIG_BOARD_EARLY_INIT_R
24#define CONFIG_LAST_STAGE_INIT
25
26#define CONFIG_FSL_ESDHC
27#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
28
29#define CONFIG_CMD_FPGAD
30#define CONFIG_CMD_IOLOOP
31
32
33
34
35#define CONFIG_83XX_CLKIN 33333333
36#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
37
38
39
40
41
42
43
44#define CONFIG_SYS_HRCW_LOW (\
45 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
46 HRCWL_DDR_TO_SCB_CLK_2X1 |\
47 HRCWL_SVCOD_DIV_2 |\
48 HRCWL_CSB_TO_CLKIN_4X1 |\
49 HRCWL_CORE_TO_CSB_3X1)
50
51
52
53
54
55
56
57#define CONFIG_SYS_HRCW_HIGH (\
58 HRCWH_PCI_HOST |\
59 HRCWH_PCI1_ARBITER_ENABLE |\
60 HRCWH_CORE_ENABLE |\
61 HRCWH_FROM_0XFFF00100 |\
62 HRCWH_BOOTSEQ_DISABLE |\
63 HRCWH_SW_WATCHDOG_DISABLE |\
64 HRCWH_ROM_LOC_LOCAL_16BIT |\
65 HRCWH_RL_EXT_LEGACY |\
66 HRCWH_TSEC1M_IN_RGMII |\
67 HRCWH_TSEC2M_IN_RGMII |\
68 HRCWH_BIG_ENDIAN)
69
70
71
72
73#define CONFIG_SYS_SICRH (\
74 SICRH_ESDHC_A_SD |\
75 SICRH_ESDHC_B_SD |\
76 SICRH_ESDHC_C_SD |\
77 SICRH_GPIO_A_GPIO |\
78 SICRH_GPIO_B_GPIO |\
79 SICRH_IEEE1588_A_GPIO |\
80 SICRH_USB |\
81 SICRH_GTM_GPIO |\
82 SICRH_IEEE1588_B_GPIO |\
83 SICRH_ETSEC2_GPIO |\
84 SICRH_GPIOSEL_1 |\
85 SICRH_TMROBI_V3P3 |\
86 SICRH_TSOBI1_V2P5 |\
87 SICRH_TSOBI2_V2P5)
88#define CONFIG_SYS_SICRL (\
89 SICRL_SPI_PF0 |\
90 SICRL_UART_PF0 |\
91 SICRL_IRQ_PF0 |\
92 SICRL_I2C2_PF0 |\
93 SICRL_ETSEC1_GTX_CLK125)
94
95
96
97
98#define CONFIG_SYS_IMMR 0xE0000000
99
100
101
102
103#define CONFIG_FSL_SERDES
104#define CONFIG_FSL_SERDES1 0xe3000
105
106
107
108
109#define CONFIG_SYS_ACR_PIPE_DEP 3
110#define CONFIG_SYS_ACR_RPTCNT 3
111#define CONFIG_SYS_SPCR_TSECEP 3
112
113
114
115
116#define CONFIG_SYS_DDR_BASE 0x00000000
117#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
118#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
119#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
120#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
121 | DDRCDR_PZ_LOZ \
122 | DDRCDR_NZ_LOZ \
123 | DDRCDR_ODT \
124 | DDRCDR_Q_DRN)
125
126
127
128
129
130
131#define CONFIG_SYS_DDR_SIZE 128
132
133#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
134#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
135 | CSCONFIG_ODT_RD_NEVER \
136 | CSCONFIG_ODT_WR_ONLY_CURRENT \
137 | CSCONFIG_BANK_BIT_3 \
138 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
139
140#define CONFIG_SYS_DDR_TIMING_3 0
141#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
142 | (0 << TIMING_CFG0_WRT_SHIFT) \
143 | (0 << TIMING_CFG0_RRT_SHIFT) \
144 | (0 << TIMING_CFG0_WWT_SHIFT) \
145 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
146 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
147 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
148 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
149
150#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
151 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
152 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
153 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
154 | (9 << TIMING_CFG1_REFREC_SHIFT) \
155 | (2 << TIMING_CFG1_WRREC_SHIFT) \
156 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
157 | (2 << TIMING_CFG1_WRTORD_SHIFT))
158
159#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
160 | (4 << TIMING_CFG2_CPO_SHIFT) \
161 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
162 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
163 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
164 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
165 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
166
167#define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
168 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
169
170#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
171 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
172 | SDRAM_CFG_DBW_16)
173
174
175#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
176#define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
177 | (0x0242 << SDRAM_MODE_SD_SHIFT))
178
179#define CONFIG_SYS_DDR_MODE2 0x00000000
180
181
182
183
184#define CONFIG_SYS_MEMTEST_START 0x00001000
185#define CONFIG_SYS_MEMTEST_END 0x07f00000
186
187
188
189
190#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
191
192#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
193#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
194
195
196
197
198#define CONFIG_SYS_INIT_RAM_LOCK 1
199#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000
200#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
201#define CONFIG_SYS_GBL_DATA_OFFSET \
202 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
203
204
205
206
207#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
208#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
209#define CONFIG_SYS_LBC_LBCR 0x00040000
210
211
212
213
214#if 1
215#define CONFIG_SYS_FLASH_CFI
216#define CONFIG_FLASH_CFI_DRIVER
217#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
218#define CONFIG_FLASH_CFI_LEGACY
219#define CONFIG_SYS_FLASH_LEGACY_512Kx16
220#endif
221
222#define CONFIG_SYS_FLASH_BASE 0xFE000000
223#define CONFIG_SYS_FLASH_SIZE 8
224#define CONFIG_SYS_FLASH_PROTECTION 1
225
226
227#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
228#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
229
230#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
231 | BR_PS_16 \
232 | BR_MS_GPCM \
233 | BR_V)
234#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
235 | OR_UPM_XAM \
236 | OR_GPCM_CSNT \
237 | OR_GPCM_ACS_DIV2 \
238 | OR_GPCM_XACS \
239 | OR_GPCM_SCY_15 \
240 | OR_GPCM_TRLX_SET \
241 | OR_GPCM_EHTR_SET)
242
243#define CONFIG_SYS_MAX_FLASH_BANKS 1
244#define CONFIG_SYS_MAX_FLASH_SECT 135
245
246#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
247#define CONFIG_SYS_FLASH_WRITE_TOUT 500
248
249
250
251
252#define CONFIG_SYS_FPGA0_BASE 0xE0600000
253#define CONFIG_SYS_FPGA0_SIZE 1
254
255
256#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE
257#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB)
258
259#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \
260 | BR_PS_16 \
261 | BR_MS_GPCM \
262 | BR_V)
263#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
264 | OR_UPM_XAM \
265 | OR_GPCM_CSNT \
266 | OR_GPCM_ACS_DIV2 \
267 | OR_GPCM_XACS \
268 | OR_GPCM_SCY_15 \
269 | OR_GPCM_TRLX_SET \
270 | OR_GPCM_EHTR_SET)
271
272#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
273#define CONFIG_SYS_FPGA_DONE(k) 0x0010
274
275#define CONFIG_SYS_FPGA_COUNT 1
276
277#define CONFIG_SYS_MCLINK_MAX 3
278
279#define CONFIG_SYS_FPGA_PTR \
280 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
281
282
283
284
285#define CONFIG_CONS_INDEX 2
286#define CONFIG_SYS_NS16550_SERIAL
287#define CONFIG_SYS_NS16550_REG_SIZE 1
288#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
289
290#define CONFIG_SYS_BAUDRATE_TABLE \
291 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
292
293#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
294#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
295
296
297
298
299#define CONFIG_SYS_I2C
300#define CONFIG_SYS_I2C_FSL
301#define CONFIG_SYS_FSL_I2C_SPEED 400000
302#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
303#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
304
305#define CONFIG_PCA953X
306#define CONFIG_PCA9698
307
308#define CONFIG_SYS_I2C_IHS
309#define CONFIG_SYS_I2C_IHS_CH0
310#define CONFIG_SYS_I2C_IHS_SPEED_0 50000
311#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
312#define CONFIG_SYS_I2C_IHS_CH1
313#define CONFIG_SYS_I2C_IHS_SPEED_1 50000
314#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
315#define CONFIG_SYS_I2C_IHS_CH2
316#define CONFIG_SYS_I2C_IHS_SPEED_2 50000
317#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
318#define CONFIG_SYS_I2C_IHS_CH3
319#define CONFIG_SYS_I2C_IHS_SPEED_3 50000
320#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
321
322#ifdef CONFIG_HRCON_DH
323#define CONFIG_SYS_I2C_IHS_DUAL
324#define CONFIG_SYS_I2C_IHS_CH0_1
325#define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000
326#define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F
327#define CONFIG_SYS_I2C_IHS_CH1_1
328#define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000
329#define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F
330#define CONFIG_SYS_I2C_IHS_CH2_1
331#define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000
332#define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F
333#define CONFIG_SYS_I2C_IHS_CH3_1
334#define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000
335#define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F
336#endif
337
338
339
340
341#define CONFIG_SYS_I2C_SOFT
342#define CONFIG_SYS_I2C_SOFT_SPEED 50000
343#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
344#define I2C_SOFT_DECLARATIONS2
345#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
346#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
347#define I2C_SOFT_DECLARATIONS3
348#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
349#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
350#define I2C_SOFT_DECLARATIONS4
351#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
352#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
353#define I2C_SOFT_DECLARATIONS5
354#define CONFIG_SYS_I2C_SOFT_SPEED_5 50000
355#define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F
356#define I2C_SOFT_DECLARATIONS6
357#define CONFIG_SYS_I2C_SOFT_SPEED_6 50000
358#define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F
359#define I2C_SOFT_DECLARATIONS7
360#define CONFIG_SYS_I2C_SOFT_SPEED_7 50000
361#define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F
362#define I2C_SOFT_DECLARATIONS8
363#define CONFIG_SYS_I2C_SOFT_SPEED_8 50000
364#define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F
365
366#ifdef CONFIG_HRCON_DH
367#define I2C_SOFT_DECLARATIONS9
368#define CONFIG_SYS_I2C_SOFT_SPEED_9 50000
369#define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F
370#define I2C_SOFT_DECLARATIONS10
371#define CONFIG_SYS_I2C_SOFT_SPEED_10 50000
372#define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F
373#define I2C_SOFT_DECLARATIONS11
374#define CONFIG_SYS_I2C_SOFT_SPEED_11 50000
375#define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F
376#define I2C_SOFT_DECLARATIONS12
377#define CONFIG_SYS_I2C_SOFT_SPEED_12 50000
378#define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F
379#endif
380
381#ifdef CONFIG_HRCON_DH
382#define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20}
383#define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8}
384#define CONFIG_HRCON_FANS { {10, 0x4c}, {11, 0x4c}, \
385 {12, 0x4c} }
386#else
387#define CONFIG_SYS_ICS8N3QV01_I2C {9, 10, 11, 12}
388#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
389#define CONFIG_HRCON_FANS { {6, 0x4c}, {7, 0x4c}, \
390 {8, 0x4c} }
391#endif
392
393#ifndef __ASSEMBLY__
394void fpga_gpio_set(unsigned int bus, int pin);
395void fpga_gpio_clear(unsigned int bus, int pin);
396int fpga_gpio_get(unsigned int bus, int pin);
397void fpga_control_set(unsigned int bus, int pin);
398void fpga_control_clear(unsigned int bus, int pin);
399#endif
400
401#define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
402#define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
403#define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4)
404
405#ifdef CONFIG_HRCON_DH
406#define I2C_ACTIVE \
407 do { \
408 if (I2C_ADAP_HWNR > 7) \
409 fpga_control_set(I2C_FPGA_IDX, 0x0004); \
410 else \
411 fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
412 } while (0)
413#else
414#define I2C_ACTIVE { }
415#endif
416#define I2C_TRISTATE { }
417#define I2C_READ \
418 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
419#define I2C_SDA(bit) \
420 do { \
421 if (bit) \
422 fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
423 else \
424 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
425 } while (0)
426#define I2C_SCL(bit) \
427 do { \
428 if (bit) \
429 fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
430 else \
431 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
432 } while (0)
433#define I2C_DELAY udelay(25)
434
435
436
437
438#define CONFIG_BITBANGMII
439#define CONFIG_BITBANGMII_MULTI
440
441
442
443
444#define CONFIG_SYS_OSD_SCREENS 1
445#define CONFIG_SYS_DP501_DIFFERENTIAL
446#define CONFIG_SYS_DP501_VCAPCTRL0 0x01
447
448#ifdef CONFIG_HRCON_DH
449#define CONFIG_SYS_OSD_DH
450#endif
451
452
453
454
455
456#define CONFIG_SYS_PCIE1_BASE 0xA0000000
457#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
458#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
459#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
460#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
461#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
462#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
463#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
464#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
465
466
467#define CONFIG_SYS_SCCR_PCIEXP1CM 1
468
469#define CONFIG_PCI_INDIRECT_BRIDGE
470#define CONFIG_PCIE
471
472#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957
473#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
474
475
476
477
478#define CONFIG_TSEC_ENET
479#define CONFIG_SYS_TSEC1_OFFSET 0x24000
480#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
481
482
483
484
485#define CONFIG_MII 1
486#define CONFIG_TSEC1
487#define CONFIG_TSEC1_NAME "eTSEC0"
488#define TSEC1_PHY_ADDR 1
489#define TSEC1_PHYIDX 0
490#define TSEC1_FLAGS TSEC_GIGABIT
491
492
493#define CONFIG_ETHPRIME "eTSEC0"
494
495
496
497
498#if 1
499#define CONFIG_ENV_IS_IN_FLASH 1
500#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
501 CONFIG_SYS_MONITOR_LEN)
502#define CONFIG_ENV_SECT_SIZE 0x10000
503#define CONFIG_ENV_SIZE 0x2000
504#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
505#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
506#else
507#define CONFIG_ENV_IS_NOWHERE
508#define CONFIG_ENV_SIZE 0x2000
509#endif
510
511#define CONFIG_LOADS_ECHO 1
512#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
513
514
515
516
517#define CONFIG_CMD_PCI
518
519#define CONFIG_CMDLINE_EDITING 1
520#define CONFIG_AUTO_COMPLETE
521
522
523
524
525#define CONFIG_SYS_LONGHELP
526#define CONFIG_SYS_LOAD_ADDR 0x2000000
527#define CONFIG_SYS_HZ 1000
528
529#define CONFIG_SYS_CBSIZE 1024
530
531
532#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
533#define CONFIG_SYS_MAXARGS 16
534#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
535
536
537
538
539
540
541#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
542
543
544
545
546#define CONFIG_SYS_HID0_INIT 0x000000000
547#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
548 HID0_ENABLE_INSTRUCTION_CACHE | \
549 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
550#define CONFIG_SYS_HID2 HID2_HBE
551
552
553
554
555
556
557#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
558 BATL_MEMCOHERENCE)
559#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
560 BATU_VS | BATU_VP)
561#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
562#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
563
564
565#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
566 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
567#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
568 BATU_VP)
569#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
570#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
571
572
573#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
574 BATL_MEMCOHERENCE)
575#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
576 BATU_VS | BATU_VP)
577#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
578 BATL_CACHEINHIBIT | \
579 BATL_GUARDEDSTORAGE)
580#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
581
582
583#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
584#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
585 BATU_VS | BATU_VP)
586#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
587#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
588
589
590
591
592
593#define CONFIG_ENV_OVERWRITE
594
595#if defined(CONFIG_TSEC_ENET)
596#define CONFIG_HAS_ETH0
597#endif
598
599#define CONFIG_BAUDRATE 115200
600
601#define CONFIG_LOADADDR 800000
602
603
604#define CONFIG_HOSTNAME hrcon
605#define CONFIG_ROOTPATH "/opt/nfsroot"
606#define CONFIG_BOOTFILE "uImage"
607
608#define CONFIG_PREBOOT
609
610#define CONFIG_EXTRA_ENV_SETTINGS \
611 "netdev=eth0\0" \
612 "consoledev=ttyS1\0" \
613 "u-boot=u-boot.bin\0" \
614 "kernel_addr=1000000\0" \
615 "fdt_addr=C00000\0" \
616 "fdtfile=hrcon.dtb\0" \
617 "load=tftp ${loadaddr} ${u-boot}\0" \
618 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
619 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
620 " +${filesize};cp.b ${fileaddr} " \
621 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
622 "upd=run load update\0" \
623
624#define CONFIG_NFSBOOTCOMMAND \
625 "setenv bootargs root=/dev/nfs rw " \
626 "nfsroot=$serverip:$rootpath " \
627 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
628 "console=$consoledev,$baudrate $othbootargs;" \
629 "tftp ${kernel_addr} $bootfile;" \
630 "tftp ${fdt_addr} $fdtfile;" \
631 "bootm ${kernel_addr} - ${fdt_addr}"
632
633#define CONFIG_MMCBOOTCOMMAND \
634 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
635 "console=$consoledev,$baudrate $othbootargs;" \
636 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
637 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
638 "bootm ${kernel_addr} - ${fdt_addr}"
639
640#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
641
642#endif
643