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15#ifndef __CONFIG_H
16#define __CONFIG_H
17
18
19
20
21
22
23
24#define CONFIG_460EX 1
25#ifdef CONFIG_DEVCONCENTER
26#define CONFIG_HOSTNAME devconcenter
27#else
28#define CONFIG_HOSTNAME intip
29#endif
30#define CONFIG_440 1
31
32#ifndef CONFIG_SYS_TEXT_BASE
33#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
34#endif
35
36
37
38
39#include "amcc-common.h"
40
41#define CONFIG_SYS_CLK_FREQ 66666667
42
43#define CONFIG_BOARD_EARLY_INIT_R 1
44#define CONFIG_MISC_INIT_R 1
45#define CONFIG_BOARD_TYPES 1
46#define CFG_ALT_MEMTEST
47
48
49
50
51
52#define CONFIG_SYS_PCI_MEMBASE 0x80000000
53#define CONFIG_SYS_PCI_BASE 0xd0000000
54#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
55
56
57#ifdef CONFIG_DEVCONCENTER
58#define CONFIG_SYS_FLASH_BASE 0xF8000000
59#define CONFIG_SYS_FLASH_SIZE (128 << 20)
60#else
61#define CONFIG_SYS_FLASH_BASE 0xFC000000
62#define CONFIG_SYS_FLASH_SIZE (64 << 20)
63#endif
64
65#define CONFIG_SYS_NVRAM_BASE 0xE0000000
66#define CONFIG_SYS_UART_BASE 0xE0100000
67#define CONFIG_SYS_IO_BASE 0xE0200000
68
69#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000
70#define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4
71#ifdef CONFIG_DEVCONCENTER
72#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xC8000000
73#else
74#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xCC000000
75#endif
76#define CONFIG_SYS_FLASH_BASE_PHYS \
77 (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) \
78 | (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
79
80#define CONFIG_SYS_OCM_BASE 0xE3000000
81#define CONFIG_SYS_SRAM_BASE 0xE8000000
82#define CONFIG_SYS_SRAM_SIZE (256 << 10)
83#define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000
84
85#define CONFIG_SYS_AHB_BASE 0xE2000000
86
87
88
89
90#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE
91#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
92#define CONFIG_SYS_GBL_DATA_OFFSET \
93 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
94#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
95
96
97
98
99#define CONFIG_CONS_INDEX 1
100
101
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104
105
106
107#define CONFIG_ENV_IS_IN_FLASH 1
108#define CONFIG_SYS_NOR_CS 0
109
110
111
112
113#define CONFIG_SYS_FLASH_CFI
114#define CONFIG_FLASH_CFI_DRIVER
115#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
116
117#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
118#define CONFIG_SYS_MAX_FLASH_BANKS 1
119#ifdef CONFIG_DEVCONCENTER
120#define CONFIG_SYS_MAX_FLASH_SECT 1024
121#else
122#define CONFIG_SYS_MAX_FLASH_SECT 512
123#endif
124
125#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
126#define CONFIG_SYS_FLASH_WRITE_TOUT 500
127
128#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
129#define CONFIG_SYS_FLASH_EMPTY_INFO
130
131#ifdef CONFIG_ENV_IS_IN_FLASH
132#define CONFIG_ENV_SECT_SIZE 0x20000
133#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
134#define CONFIG_ENV_SIZE 0x4000
135
136
137#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
138#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
139#endif
140
141
142
143
144
145#define CONFIG_AUTOCALIB "silent\0"
146
147#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION
148#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION
149#undef CONFIG_PPC4xx_DDR_METHOD_A
150
151
152
153#define CONFIG_SYS_SDRAM_R0BAS 0x0000f800
154#define CONFIG_SYS_SDRAM_R1BAS 0x00000000
155#define CONFIG_SYS_SDRAM_R2BAS 0x00000000
156#define CONFIG_SYS_SDRAM_R3BAS 0x00000000
157#define CONFIG_SYS_SDRAM_PLBADDULL 0x00000000
158#define CONFIG_SYS_SDRAM_PLBADDUHB 0x00000008
159#define CONFIG_SYS_SDRAM_CONF1LL 0x80001C00
160#define CONFIG_SYS_SDRAM_CONF1HB 0x80001C80
161#define CONFIG_SYS_SDRAM_CONFPATHB 0x10a68000
162
163
164#define CONFIG_SYS_SDRAM0_MB0CF 0x00000201
165#define CONFIG_SYS_SDRAM0_MB1CF 0x00000000
166#define CONFIG_SYS_SDRAM0_MB2CF 0x00000000
167#define CONFIG_SYS_SDRAM0_MB3CF 0x00000000
168#define CONFIG_SYS_SDRAM0_MCOPT1 0x05120000
169#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000
170#define CONFIG_SYS_SDRAM0_MODT0 0x00000000
171#define CONFIG_SYS_SDRAM0_MODT1 0x00000000
172#define CONFIG_SYS_SDRAM0_MODT2 0x00000000
173#define CONFIG_SYS_SDRAM0_MODT3 0x00000000
174#define CONFIG_SYS_SDRAM0_CODT 0x00000020
175#define CONFIG_SYS_SDRAM0_RTR 0x06180000
176#define CONFIG_SYS_SDRAM0_INITPLR0 0xA8380000
177#define CONFIG_SYS_SDRAM0_INITPLR1 0x81900400
178#define CONFIG_SYS_SDRAM0_INITPLR2 0x81020000
179#define CONFIG_SYS_SDRAM0_INITPLR3 0x81030000
180#define CONFIG_SYS_SDRAM0_INITPLR4 0x81010002
181#define CONFIG_SYS_SDRAM0_INITPLR5 0xE4000552
182#define CONFIG_SYS_SDRAM0_INITPLR6 0x81900400
183#define CONFIG_SYS_SDRAM0_INITPLR7 0x8A880000
184#define CONFIG_SYS_SDRAM0_INITPLR8 0x8A880000
185#define CONFIG_SYS_SDRAM0_INITPLR9 0x8A880000
186#define CONFIG_SYS_SDRAM0_INITPLR10 0x8A880000
187#define CONFIG_SYS_SDRAM0_INITPLR11 0x81000452
188#define CONFIG_SYS_SDRAM0_INITPLR12 0x81010382
189#define CONFIG_SYS_SDRAM0_INITPLR13 0x81010002
190#define CONFIG_SYS_SDRAM0_INITPLR14 0x00000000
191#define CONFIG_SYS_SDRAM0_INITPLR15 0x00000000
192#define CONFIG_SYS_SDRAM0_RQDC 0x80000038
193#define CONFIG_SYS_SDRAM0_RFDC 0x00000257
194#define CONFIG_SYS_SDRAM0_RDCC 0x40000000
195#define CONFIG_SYS_SDRAM0_DLCR 0x00000000
196#define CONFIG_SYS_SDRAM0_CLKTR 0x40000000
197#define CONFIG_SYS_SDRAM0_WRDTR 0x86000823
198#define CONFIG_SYS_SDRAM0_SDTR1 0x80201000
199#define CONFIG_SYS_SDRAM0_SDTR2 0x32204232
200#define CONFIG_SYS_SDRAM0_SDTR3 0x090C0D15
201#define CONFIG_SYS_SDRAM0_MMODE 0x00000452
202#define CONFIG_SYS_SDRAM0_MEMODE 0x00000002
203
204#define CONFIG_SYS_MBYTES_SDRAM 256
205
206
207
208
209#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
210
211#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
212#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
213#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
214#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
215
216
217#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x54
218#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
219#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
220
221
222#define CONFIG_DTT_LM63 1
223#define CONFIG_DTT_SENSORS { 0 }
224#define CONFIG_DTT_PWM_LOOKUPTABLE \
225 { { 40, 10 }, { 50, 20 }, { 60, 40 } }
226#define CONFIG_DTT_TACH_LIMIT 0xa10
227
228
229#define CONFIG_RTC_DS1337 1
230#define CONFIG_SYS_I2C_RTC_ADDR 0x68
231
232
233
234
235#define CONFIG_IBM_EMAC4_V4 1
236
237#define CONFIG_HAS_ETH0
238#define CONFIG_HAS_ETH1
239
240#define CONFIG_PHY_ADDR 2
241#define CONFIG_PHY1_ADDR 3
242
243#define CONFIG_PHY_RESET 1
244#define CONFIG_PHY_GIGE 1
245#define CONFIG_PHY_DYNAMIC_ANEG 1
246
247
248
249
250#define CONFIG_USB_OHCI_NEW
251#undef CONFIG_SYS_OHCI_BE_CONTROLLER
252#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
253#define CONFIG_SYS_OHCI_USE_NPS
254#define CONFIG_SYS_USB_OHCI_REGS_BASE (CONFIG_SYS_AHB_BASE | 0xd0000)
255#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
256#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
257
258
259
260
261#define CONFIG_EXTRA_ENV_SETTINGS \
262 CONFIG_AMCC_DEF_ENV \
263 CONFIG_AMCC_DEF_ENV_POWERPC \
264 CONFIG_AMCC_DEF_ENV_NOR_UPD \
265 "kernel_addr=fc000000\0" \
266 "fdt_addr=fc1e0000\0" \
267 "ramdisk_addr=fc200000\0" \
268 "pciconfighost=1\0" \
269 "pcie_mode=RP:RP\0" \
270 ""
271
272
273
274
275#define CONFIG_CMD_CHIP_CONFIG
276#define CONFIG_CMD_DATE
277#define CONFIG_CMD_DTT
278#define CONFIG_CMD_PCI
279#define CONFIG_CMD_SDRAM
280
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285
286
287#define CONFIG_PCI_INDIRECT_BRIDGE
288#define CONFIG_PCI_SCAN_SHOW
289#define CONFIG_PCI_CONFIG_HOST_BRIDGE
290#define CONFIG_PCI_DISABLE_PCIE
291
292
293#define CONFIG_SYS_PCI_TARGET_INIT
294#undef CONFIG_SYS_PCI_MASTER_INIT
295
296#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014
297#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe
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312
313
314#define CONFIG_SYS_EBC_PB0AP 0x10055e00
315#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
316
317
318#define CONFIG_SYS_EBC_PB1AP 0x02815480
319
320#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_NVRAM_BASE | 0x18000)
321
322
323#define CONFIG_SYS_EBC_PB2AP 0x02815480
324
325#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_UART_BASE | 0x1A000)
326
327
328#define CONFIG_SYS_EBC_PB3AP 0x02815480
329
330#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_IO_BASE | 0x1A000)
331
332
333
334
335
336#define CONFIG_SYS_4xx_GPIO_TABLE { \
337{ \
338 \
339{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
340{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
341{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
342{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
343{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
344{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
345{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
346{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
347{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
348{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
349{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
350{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
351{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
352{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
353{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
354{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
355{GPIO0_BASE, GPIO_IN , GPIO_SEL, GPIO_OUT_0}, \
356{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
357{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
358{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, \
359{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
360{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
361{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
362{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
363{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
364{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
365{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
366{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
367{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
368{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
369{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, \
370{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, \
371}, \
372{ \
373 \
374{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, \
375{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, \
376{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, \
377{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, \
378{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, \
379{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, \
380{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, \
381{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, \
382{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
383{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
384{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
385{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
386{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, \
387{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, \
388{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
389{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
390{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
391{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
392{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
393{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, \
394{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, \
395{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
396{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, \
397{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, \
398{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, \
399{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
400{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
401{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
402{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
403{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, \
404{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, \
405{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
406} \
407}
408
409#endif
410