1
2
3
4
5
6
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11#define CONFIG_405EP 1
12#define CONFIG_IOCON 1
13
14#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
15
16
17
18
19#define CONFIG_HOSTNAME iocon
20#include "amcc-common.h"
21
22
23#undef CONFIG_SYS_LONGHELP
24
25#define CONFIG_BOARD_EARLY_INIT_R
26#define CONFIG_LAST_STAGE_INIT
27
28#define CONFIG_SYS_CLK_FREQ 33333333
29
30
31
32
33#define PLLMR0_DEFAULT PLLMR0_266_133_66
34#define PLLMR1_DEFAULT PLLMR1_266_133_66
35
36
37#define CONFIG_FIT_DISABLE_SHA256
38
39#define CONFIG_ENV_IS_IN_FLASH
40
41
42
43
44#define CONFIG_EXTRA_ENV_SETTINGS \
45 CONFIG_AMCC_DEF_ENV \
46 CONFIG_AMCC_DEF_ENV_POWERPC \
47 CONFIG_AMCC_DEF_ENV_NOR_UPD \
48 "kernel_addr=fc000000\0" \
49 "fdt_addr=fc1e0000\0" \
50 "ramdisk_addr=fc200000\0" \
51 ""
52
53#define CONFIG_PHY_ADDR 4
54#define CONFIG_HAS_ETH0
55#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
56
57
58
59
60#define CONFIG_CMD_FPGAD
61#undef CONFIG_CMD_EEPROM
62#undef CONFIG_CMD_IRQ
63
64
65
66
67#define CONFIG_SDRAM_BANK0 1
68
69
70#define CONFIG_SYS_SDRAM_CL 3
71#define CONFIG_SYS_SDRAM_tRP 20
72#define CONFIG_SYS_SDRAM_tRC 66
73#define CONFIG_SYS_SDRAM_tRCD 20
74#define CONFIG_SYS_SDRAM_tRFC 66
75
76
77
78
79
80
81
82
83
84
85#define CONFIG_CONS_INDEX 1
86#undef CONFIG_SYS_EXT_SERIAL_CLOCK
87#undef CONFIG_SYS_405_UART_ERRATA_59
88#define CONFIG_SYS_BASE_BAUD 691200
89
90
91
92
93#define CONFIG_SYS_I2C
94#define CONFIG_SYS_I2C_PPC4XX
95#define CONFIG_SYS_I2C_PPC4XX_CH0
96#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
97#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
98#define CONFIG_SYS_I2C_IHS
99
100#define CONFIG_SYS_I2C_SPEED 400000
101#define CONFIG_SYS_SPD_BUS_NUM 4
102
103#define CONFIG_PCA953X
104#define CONFIG_PCA9698
105
106#define CONFIG_SYS_I2C_IHS_CH0
107#define CONFIG_SYS_I2C_IHS_SPEED_0 50000
108#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
109#define CONFIG_SYS_I2C_IHS_CH1
110#define CONFIG_SYS_I2C_IHS_SPEED_1 50000
111#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
112#define CONFIG_SYS_I2C_IHS_CH2
113#define CONFIG_SYS_I2C_IHS_SPEED_2 50000
114#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
115#define CONFIG_SYS_I2C_IHS_CH3
116#define CONFIG_SYS_I2C_IHS_SPEED_3 50000
117#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
118
119
120
121
122#define CONFIG_SYS_I2C_SOFT
123#define CONFIG_SYS_I2C_SOFT_SPEED 50000
124#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
125#define I2C_SOFT_DECLARATIONS2
126#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
127#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
128#define I2C_SOFT_DECLARATIONS3
129#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
130#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
131#define I2C_SOFT_DECLARATIONS4
132#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
133#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
134
135#define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8}
136#define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8}
137#define CONFIG_SYS_DP501_I2C {0, 1, 2, 3}
138
139#ifndef __ASSEMBLY__
140void fpga_gpio_set(unsigned int bus, int pin);
141void fpga_gpio_clear(unsigned int bus, int pin);
142int fpga_gpio_get(unsigned int bus, int pin);
143#endif
144
145#define I2C_ACTIVE { }
146#define I2C_TRISTATE { }
147#define I2C_READ \
148 (fpga_gpio_get(I2C_ADAP_HWNR, 0x0040) ? 1 : 0)
149#define I2C_SDA(bit) \
150 do { \
151 if (bit) \
152 fpga_gpio_set(I2C_ADAP_HWNR, 0x0040); \
153 else \
154 fpga_gpio_clear(I2C_ADAP_HWNR, 0x0040); \
155 } while (0)
156#define I2C_SCL(bit) \
157 do { \
158 if (bit) \
159 fpga_gpio_set(I2C_ADAP_HWNR, 0x0020); \
160 else \
161 fpga_gpio_clear(I2C_ADAP_HWNR, 0x0020); \
162 } while (0)
163#define I2C_DELAY udelay(25)
164
165
166
167
168#define CONFIG_SYS_FLASH_CFI
169#define CONFIG_FLASH_CFI_DRIVER
170
171#define CONFIG_SYS_FLASH_BASE 0xFC000000
172#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
173
174#define CONFIG_SYS_MAX_FLASH_BANKS 1
175#define CONFIG_SYS_MAX_FLASH_SECT 512
176
177#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
178#define CONFIG_SYS_FLASH_WRITE_TOUT 500
179
180#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
181
182#define CONFIG_SYS_FLASH_EMPTY_INFO
183#define CONFIG_SYS_FLASH_QUIET_TEST 1
184
185#ifdef CONFIG_ENV_IS_IN_FLASH
186#define CONFIG_ENV_SECT_SIZE 0x20000
187#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
188#define CONFIG_ENV_SIZE 0x2000
189
190
191#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
192#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
193#endif
194
195
196
197
198#define CONFIG_SYS_4xx_GPIO_TABLE { \
199{ \
200 \
201{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
202{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
203{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
204{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
205{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
206{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, \
207{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
208{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
209{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
210{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
211{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
212{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
213{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
214{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
215{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
216{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
217{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
218{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
219{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
220{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
221{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
222{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
223{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
224{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
225{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
226{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
227{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
228{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
229{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
230{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
231{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
232{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
233} \
234}
235
236
237
238
239
240#define CONFIG_SYS_TEMP_STACK_OCM 1
241
242
243#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
244#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
245#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
246#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
247
248#define CONFIG_SYS_GBL_DATA_OFFSET \
249 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
250#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
251
252
253
254
255
256
257#define CONFIG_SYS_EBC_PB0AP 0xa382a880
258#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000
259
260
261#define CONFIG_SYS_EBC_PB1AP 0x92015480
262#define CONFIG_SYS_EBC_PB1CR 0xFB858000
263
264
265#define CONFIG_SYS_FPGA0_BASE 0x7f100000
266#define CONFIG_SYS_EBC_PB2AP 0x02825080
267#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA0_BASE | 0x1a000)
268
269#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
270#define CONFIG_SYS_FPGA_DONE(k) 0x0010
271
272#define CONFIG_SYS_FPGA_COUNT 1
273
274#define CONFIG_SYS_MCLINK_MAX 3
275
276#define CONFIG_SYS_FPGA_PTR \
277 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
278
279
280#define CONFIG_SYS_LATCH_BASE 0x7f200000
281#define CONFIG_SYS_EBC_PB3AP 0x02025080
282#define CONFIG_SYS_EBC_PB3CR 0x7f21a000
283
284#define CONFIG_SYS_LATCH0_RESET 0xffef
285#define CONFIG_SYS_LATCH0_BOOT 0xffff
286#define CONFIG_SYS_LATCH1_RESET 0xffff
287#define CONFIG_SYS_LATCH1_BOOT 0xffff
288
289
290
291
292#define CONFIG_SYS_MPC92469AC
293#define CONFIG_SYS_OSD_SCREENS 1
294#define CONFIG_SYS_DP501_DIFFERENTIAL
295#define CONFIG_SYS_DP501_VCAPCTRL0 0x01
296
297#define CONFIG_BITBANGMII
298#define CONFIG_BITBANGMII_MULTI
299
300#endif
301