1/* 2 * (C) Copyright 2006 3 * MicroSys GmbH 4 * 5 * (C) Copyright 2009 6 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11#ifndef __CONFIG_H 12#define __CONFIG_H 13 14/* 15 * High Level Configuration Options 16 */ 17 18#define CONFIG_MPC5200 19#define CONFIG_MPX5200 1 /* MPX5200 board */ 20#define CONFIG_MPC5200_DDR 1 /* use DDR RAM */ 21#define CONFIG_IPEK01 /* Motherboard is ipek01 */ 22 23#define CONFIG_SYS_TEXT_BASE 0xfc000000 24 25#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */ 26 27#define CONFIG_MISC_INIT_R 28 29#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ 30#ifdef CONFIG_CMD_KGDB 31#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 32#endif 33 34/* 35 * Serial console configuration 36 */ 37#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ 38#define CONFIG_BAUDRATE 115200 /* ... at 9600 bps */ 39#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } 40 41#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 42 43/* 44 * Video configuration for LIME GDC 45 */ 46#ifdef CONFIG_VIDEO 47#define CONFIG_VIDEO_MB862xx 48#define CONFIG_VIDEO_MB862xx_ACCEL 49#define VIDEO_FB_16BPP_WORD_SWAP 50#define CONFIG_VIDEO_LOGO 51#define CONFIG_VIDEO_BMP_LOGO 52#define CONFIG_SPLASH_SCREEN 53#define CONFIG_VIDEO_BMP_GZIP 54#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */ 55/* Lime clock frequency */ 56#define CONFIG_SYS_MB862xx_CCF 0x90000 /* geo 166MHz other 133MHz */ 57/* SDRAM parameter */ 58#define CONFIG_SYS_MB862xx_MMR 0x41c767e3 59#endif 60 61/* 62 * PCI Mapping: 63 * 0x40000000 - 0x4fffffff - PCI Memory 64 * 0x50000000 - 0x50ffffff - PCI IO Space 65 */ 66#define CONFIG_PCI_SCAN_SHOW 1 67 68#define CONFIG_PCI_MEM_BUS 0x40000000 69#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 70#define CONFIG_PCI_MEM_SIZE 0x10000000 71 72#define CONFIG_PCI_IO_BUS 0x50000000 73#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 74#define CONFIG_PCI_IO_SIZE 0x01000000 75 76#define CONFIG_MII 1 77#define CONFIG_EEPRO100 1 78#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ 79 80/* USB */ 81#define CONFIG_USB_OHCI_NEW 82#define CONFIG_SYS_OHCI_BE_CONTROLLER 83 84#define CONFIG_SYS_USB_OHCI_CPU_INIT 85#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB 86#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200" 87#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 88 89/* 90 * Command line configuration. 91 */ 92#ifdef CONFIG_VIDEO 93#define CONFIG_CMD_BMP /* BMP support */ 94#endif 95#define CONFIG_CMD_DATE /* support for RTC, date/time...*/ 96#define CONFIG_CMD_IDE /* IDE harddisk support */ 97#define CONFIG_CMD_IRQ /* irqinfo */ 98#define CONFIG_CMD_PCI /* pciinfo */ 99 100#define CONFIG_SYS_LOWBOOT 1 101 102/* 103 * Autobooting 104 */ 105 106#define CONFIG_PREBOOT "echo;" \ 107 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 108 "echo" 109 110#undef CONFIG_BOOTARGS 111 112#define CONFIG_EXTRA_ENV_SETTINGS \ 113 "netdev=eth0\0" \ 114 "consoledev=ttyPSC0\0" \ 115 "hostname=ipek01\0" \ 116 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 117 "nfsroot=${serverip}:${rootpath}\0" \ 118 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 119 "addip=setenv bootargs ${bootargs} " \ 120 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 121 ":${hostname}:${netdev}:off panic=1\0" \ 122 "addtty=setenv bootargs ${bootargs} " \ 123 "console=${consoledev},${baudrate}\0" \ 124 "flash_nfs=run nfsargs addip addtty;" \ 125 "bootm ${kernel_addr} - ${fdtaddr}\0" \ 126 "flash_self=run ramargs addip addtty;" \ 127 "bootm ${kernel_addr} ${ramdisk_addr} ${fdtaddr}\0" \ 128 "net_nfs=tftp 200000 ${bootfile}; tftp ${fdtaddr} ${fdtfile};" \ 129 "run nfsargs addip addtty;" \ 130 "bootm ${loadaddr} - ${fdtaddr}\0" \ 131 "rootpath=/opt/eldk/ppc_6xx\0" \ 132 "bootfile=ipek01/uImage\0" \ 133 "load=tftp 100000 ipek01/u-boot.bin\0" \ 134 "update=protect off FC000000 +60000; era FC000000 +60000; " \ 135 "cp.b 100000 FC000000 ${filesize}\0" \ 136 "upd=run load;run update\0" \ 137 "fdtaddr=800000\0" \ 138 "loadaddr=400000\0" \ 139 "fdtfile=ipek01/ipek01.dtb\0" \ 140 "" 141 142#define CONFIG_BOOTCOMMAND "run flash_self" 143 144/* 145 * IPB Bus clocking configuration. 146 */ 147#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* for 133MHz */ 148/* PCI clock must be 33, because board will not boot */ 149#undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for 66MHz */ 150 151/* 152 * Open firmware flat tree support 153 */ 154#define OF_CPU "PowerPC,5200@0" 155#define OF_SOC "soc5200@f0000000" 156#define OF_TBCLK (bd->bi_busfreq / 4) 157 158/* 159 * I2C configuration 160 */ 161#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ 162#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ 163 164#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ 165#define CONFIG_SYS_I2C_SLAVE 0x7F 166 167/* 168 * EEPROM configuration 169 */ 170#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 171#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 172#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 173#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 174 175/* 176 * RTC configuration 177 */ 178#define CONFIG_RTC_PCF8563 179#define CONFIG_SYS_I2C_RTC_ADDR 0x51 180 181#define CONFIG_SYS_FLASH_BASE 0xFC000000 182#define CONFIG_SYS_FLASH_SIZE 0x01000000 183#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ 184 CONFIG_SYS_MONITOR_LEN) 185 186#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ 187#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ 188#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 189 190/* use CFI flash driver */ 191#define CONFIG_FLASH_CFI_DRIVER 192#define CONFIG_SYS_FLASH_CFI 193#define CONFIG_SYS_FLASH_EMPTY_INFO 194#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 195 196/* 197 * Environment settings 198 */ 199#define CONFIG_ENV_IS_IN_FLASH 1 200#define CONFIG_ENV_SIZE 0x10000 201#define CONFIG_ENV_SECT_SIZE 0x20000 202#define CONFIG_ENV_OVERWRITE 1 203#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 204#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 205 206/* 207 * Memory map 208 */ 209#define CONFIG_SYS_MBAR 0xf0000000 210#define CONFIG_SYS_SDRAM_BASE 0x00000000 211#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 212#define CONFIG_SYS_SRAM_BASE 0xF1000000 213#define CONFIG_SYS_SRAM_SIZE 0x00200000 214#define CONFIG_SYS_LIME_BASE 0xE4000000 215#define CONFIG_SYS_LIME_SIZE 0x04000000 216#define CONFIG_SYS_FPGA_BASE 0xC0000000 217#define CONFIG_SYS_FPGA_SIZE 0x10000000 218#define CONFIG_SYS_MPEG_BASE 0xe2000000 219#define CONFIG_SYS_MPEG_SIZE 0x01000000 220#define CONFIG_SYS_CF_BASE 0xe1000000 221#define CONFIG_SYS_CF_SIZE 0x01000000 222 223/* Use SRAM until RAM will be available */ 224#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM 225/* End of used area in DPRAM */ 226#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE 227 228#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 229 GENERATED_GBL_DATA_SIZE) 230#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 231 232#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 233#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 234# define CONFIG_SYS_RAMBOOT 1 235#endif 236 237#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ 238#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 128 kB for malloc() */ 239#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 240 241/* 242 * Ethernet configuration 243 */ 244#define CONFIG_MPC5xxx_FEC 1 245#define CONFIG_MPC5xxx_FEC_MII100 246#define CONFIG_PHY_ADDR 0x00 247 248/* 249 * GPIO configuration 250 */ 251#define CONFIG_SYS_GPS_PORT_CONFIG 0x1d556624 252 253/* 254 * Miscellaneous configurable options 255 */ 256#define CONFIG_SYS_LONGHELP /* undef to save memory */ 257#ifdef CONFIG_CMD_KGDB 258#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 259#else 260#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 261#endif 262/* Print Buffer Size */ 263#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 264 sizeof(CONFIG_SYS_PROMPT) + 16) 265/* max number of command args */ 266#define CONFIG_SYS_MAXARGS 16 267/* Boot Argument Buffer Size */ 268#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 269 270#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ 271#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1...15 MB in DRAM */ 272 273#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 274 275/* 276 * Various low-level settings 277 */ 278#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI 279#define CONFIG_SYS_HID0_FINAL HID0_ICE 280 281#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE 282#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE 283#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE 284#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE 285#define CONFIG_SYS_CS1_START CONFIG_SYS_SRAM_BASE 286#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_SRAM_SIZE 287#define CONFIG_SYS_CS3_START CONFIG_SYS_LIME_BASE 288#define CONFIG_SYS_CS3_SIZE CONFIG_SYS_LIME_SIZE 289#define CONFIG_SYS_CS6_START CONFIG_SYS_FPGA_BASE 290#define CONFIG_SYS_CS6_SIZE CONFIG_SYS_FPGA_SIZE 291#define CONFIG_SYS_CS5_START CONFIG_SYS_CF_BASE 292#define CONFIG_SYS_CS5_SIZE CONFIG_SYS_CF_SIZE 293#define CONFIG_SYS_CS7_START CONFIG_SYS_MPEG_BASE 294#define CONFIG_SYS_CS7_SIZE CONFIG_SYS_MPEG_SIZE 295 296#ifdef CONFIG_SYS_PCISPEED_66 297#define CONFIG_SYS_BOOTCS_CFG 0x0006F900 298#define CONFIG_SYS_CS1_CFG 0x0004FB00 299#define CONFIG_SYS_CS2_CFG 0x0006F900 300#else 301#define CONFIG_SYS_BOOTCS_CFG 0x0002F900 302#define CONFIG_SYS_CS1_CFG 0x0001FB00 303#define CONFIG_SYS_CS2_CFG 0x0002F90C 304#endif 305 306/* 307 * Ack active, Muxed mode, AS=24 bit address, DS=32 bit data, 0 308 * waitstates, writeswap and readswap enabled 309 */ 310#define CONFIG_SYS_CS3_CFG 0x00FFFB0C 311#define CONFIG_SYS_CS6_CFG 0x00FFFB0C 312#define CONFIG_SYS_CS7_CFG 0x4040751C 313 314#define CONFIG_SYS_CS_BURST 0x00000000 315#define CONFIG_SYS_CS_DEADCYCLE 0x33330000 316 317#define CONFIG_SYS_RESET_ADDRESS 0xff000000 318 319/*----------------------------------------------------------------------- 320 * USB stuff 321 *----------------------------------------------------------------------- 322 */ 323#define CONFIG_USB_CLOCK 0x0001BBBB 324#define CONFIG_USB_CONFIG 0x00005000 325 326/*----------------------------------------------------------------------- 327 * IDE/ATA stuff Supports IDE harddisk 328 *----------------------------------------------------------------------- 329 */ 330#define CONFIG_IDE_PREINIT 331 332#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 333#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ 334 335#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 336 337#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA 338 339/* Offset for data I/O */ 340#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) 341 342/* Offset for normal register accesses */ 343#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) 344 345/* Offset for alternate registers */ 346#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) 347 348/* Interval between registers */ 349#define CONFIG_SYS_ATA_STRIDE 4 350 351#endif /* __CONFIG_H */ 352