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8#ifndef _CONFIG_KMP204X_H
9#define _CONFIG_KMP204X_H
10
11#define CONFIG_SYS_TEXT_BASE 0xfff40000
12
13#define CONFIG_KM_DEF_NETDEV "netdev=eth0\0"
14
15
16
17#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048"
18
19#define CONFIG_NAND_ECC_BCH
20
21
22#include "keymile-common.h"
23
24#define CONFIG_SYS_RAMBOOT
25#define CONFIG_RAMBOOT_PBL
26#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
27#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
28#define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg
29#define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg
30
31
32#define CONFIG_SYS_BOOK3E_HV
33#define CONFIG_FSL_CORENET
34#define CONFIG_MP
35
36#define CONFIG_SYS_FSL_CPC
37#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
38#define CONFIG_PCIE1
39#define CONFIG_PCIE3
40#define CONFIG_FSL_PCI_INIT
41#define CONFIG_SYS_PCI_64BIT
42
43#define CONFIG_SYS_DPAA_RMAN
44
45
46#define CONFIG_SYS_EXTRA_ENV_RELOC
47#define CONFIG_ENV_IS_IN_SPI_FLASH
48#define CONFIG_ENV_SPI_BUS 0
49#define CONFIG_ENV_SPI_CS 0
50#define CONFIG_ENV_SPI_MAX_HZ 20000000
51#define CONFIG_ENV_SPI_MODE 0
52#define CONFIG_ENV_OFFSET 0x100000
53#define CONFIG_ENV_SIZE 0x004000
54#define CONFIG_ENV_SECT_SIZE 0x010000
55#define CONFIG_ENV_OFFSET_REDUND 0x110000
56#define CONFIG_ENV_TOTAL_SIZE 0x020000
57
58#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
59
60#ifndef __ASSEMBLY__
61unsigned long get_board_sys_clk(unsigned long dummy);
62#endif
63#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
64
65
66
67
68#define CONFIG_SYS_CACHE_STASHING
69#define CONFIG_BACKSIDE_L2_CACHE
70#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
71#define CONFIG_BTB
72
73#define CONFIG_ENABLE_36BIT_PHYS
74
75#define CONFIG_ADDR_MAP
76#define CONFIG_SYS_NUM_ADDR_MAP 64
77
78#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS
79
80
81
82
83#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
84#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
85 CONFIG_RAMBOOT_TEXT_BASE)
86#define CONFIG_SYS_L3_SIZE (1024 << 10)
87#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
88
89#define CONFIG_SYS_DCSRBAR 0xf0000000
90#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
91
92
93
94
95#define CONFIG_VERY_BIG_RAM
96#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
97#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
98
99#define CONFIG_DIMM_SLOTS_PER_CTLR 1
100#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
101
102#define CONFIG_DDR_SPD
103#define CONFIG_FSL_DDR_INTERACTIVE
104
105#define CONFIG_SYS_SPD_BUS_NUM 0
106#define SPD_EEPROM_ADDRESS 0x54
107#define CONFIG_SYS_SDRAM_SIZE 4096
108
109#define CONFIG_SYS_LOAD_ADDR 0x100000
110#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
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122
123
124
125
126#define CONFIG_KM_ROOTFSSIZE 0x0
127
128#define CONFIG_KM_PNVRAM 0x80000
129
130#define CONFIG_KM_PHRAM 0x100000
131
132
133#define CONFIG_KM_RESERVED_PRAM 0x1000
134
135
136#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10)
137
138#define CONFIG_KM_CRAMFS_ADDR 0x2000000
139#define CONFIG_KM_KERNEL_ADDR 0x1000000
140#define CONFIG_KM_FDT_ADDR 0x1F80000
141
142
143
144
145
146
147#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_2)
148
149
150#define CONFIG_NAND_FSL_ELBC
151#define CONFIG_SYS_NAND_BASE 0xffa00000
152#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
153
154#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
155#define CONFIG_SYS_MAX_NAND_DEVICE 1
156#define CONFIG_CMD_NAND
157#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
158
159#define CONFIG_BCH
160
161
162#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
163 | BR_PS_8 \
164 | BR_MS_FCM \
165 | BR_V)
166
167#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB \
168 | OR_FCM_BCTLD \
169 | OR_FCM_SCY_1 \
170 | OR_FCM_RST \
171 | OR_FCM_PGS \
172 | OR_FCM_CST)
173
174#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
175#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
176
177
178#define CONFIG_SYS_QRIO_BASE 0xfb000000
179#define CONFIG_SYS_QRIO_BASE_PHYS 0xffb000000ull
180
181#define CONFIG_SYS_QRIO_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \
182 | BR_PS_8 \
183 | BR_DECC_OFF \
184 | BR_MS_GPCM \
185 | BR_V)
186
187#define CONFIG_SYS_QRIO_OR_PRELIM (OR_AM_64KB \
188 | OR_GPCM_BCTLD \
189 | OR_GPCM_ACS_DIV4 \
190 | OR_GPCM_SCY_2 \
191 | OR_GPCM_TRLX \
192 | OR_GPCM_EAD)
193
194#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM
195#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM
196
197
198#define CONFIG_BOOTCOUNT_LIMIT
199#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_QRIO_BASE + 0x20)
200
201#define CONFIG_BOARD_EARLY_INIT_R
202#define CONFIG_MISC_INIT_F
203#define CONFIG_MISC_INIT_R
204#define CONFIG_LAST_STAGE_INIT
205
206#define CONFIG_HWCONFIG
207
208
209#define CONFIG_L1_INIT_RAM
210#define CONFIG_SYS_INIT_RAM_LOCK
211#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
212#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
213#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
214
215#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
216 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
217 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
218#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
219
220#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
221 GENERATED_GBL_DATA_SIZE)
222#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
223
224#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
225#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
226#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
227
228
229
230
231
232#define CONFIG_CONS_INDEX 1
233#define CONFIG_SYS_NS16550_SERIAL
234#define CONFIG_SYS_NS16550_REG_SIZE 1
235#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
236
237#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
238#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
239#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
240#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
241
242#define CONFIG_KM_CONSOLE_TTY "ttyS0"
243
244
245
246#define CONFIG_SYS_I2C
247#define CONFIG_SYS_I2C_INIT_BOARD
248#define CONFIG_SYS_I2C_SPEED 100000
249#define CONFIG_SYS_NUM_I2C_BUSES 3
250#define CONFIG_SYS_I2C_MAX_HOPS 1
251#define CONFIG_SYS_I2C_FSL
252#define CONFIG_I2C_MULTI_BUS
253#define CONFIG_I2C_CMD_TREE
254#define CONFIG_SYS_FSL_I2C_SPEED 400000
255#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
256#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
257#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
258 {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
259 {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \
260 }
261#ifndef __ASSEMBLY__
262void set_sda(int state);
263void set_scl(int state);
264int get_sda(void);
265int get_scl(void);
266#endif
267
268#define CONFIG_KM_IVM_BUS 1
269
270
271
272
273#define CONFIG_SPI_FLASH_BAR
274#define CONFIG_SF_DEFAULT_SPEED 20000000
275#define CONFIG_SF_DEFAULT_MODE 0
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277
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279
280
281
282
283#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
284#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
285#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
286#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
287#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
288#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
289#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
290#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
291
292
293#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
294#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
295#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
296#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000
297#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8010000
298#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
299#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8010000ull
300#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
301
302
303#define CONFIG_SYS_DPAA_QBMAN
304#define CONFIG_SYS_BMAN_NUM_PORTALS 10
305#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
306#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
307#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
308#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
309#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
310#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
311#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
312#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
313 CONFIG_SYS_BMAN_CENA_SIZE)
314#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
315#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
316#define CONFIG_SYS_QMAN_NUM_PORTALS 10
317#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
318#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
319#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
320#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
321#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
322#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
323#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
324#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
325 CONFIG_SYS_QMAN_CENA_SIZE)
326#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
327#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
328
329#define CONFIG_SYS_DPAA_FMAN
330#define CONFIG_SYS_DPAA_PME
331
332
333
334
335#define CONFIG_SYS_QE_FW_IN_SPIFLASH
336#define CONFIG_SYS_FMAN_FW_ADDR 0x120000
337#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
338#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
339
340#define CONFIG_FMAN_ENET
341#define CONFIG_PHYLIB_10G
342#define CONFIG_PHY_MARVELL
343
344#define CONFIG_PCI_INDIRECT_BRIDGE
345
346#define CONFIG_PCI_SCAN_SHOW
347
348
349#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11
350#define CONFIG_SYS_TBIPA_VALUE 8
351#define CONFIG_PHYLIB
352#define CONFIG_ETHPRIME "FM1@DTSEC5"
353#define CONFIG_PHY_GIGE
354
355
356
357
358#define CONFIG_LOADS_ECHO
359#define CONFIG_SYS_LOADS_BAUD_CHANGE
360
361
362
363
364#define CONFIG_WATCHDOG
365#define CONFIG_WATCHDOG_PRESC 34
366#define CONFIG_WATCHDOG_RC WRC_CHIP
367
368
369
370
371
372#define CONFIG_CMD_PCI
373#define CONFIG_CMD_ERRATA
374
375
376#undef CONFIG_FLASH_CFI_MTD
377#undef CONFIG_JFFS2_CMDLINE
378
379
380
381
382
383
384#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
385#define CONFIG_SYS_BOOTM_LEN (64 << 20)
386
387#ifdef CONFIG_CMD_KGDB
388#define CONFIG_KGDB_BAUDRATE 230400
389#endif
390
391#define __USB_PHY_TYPE utmi
392#define CONFIG_USB_EHCI_FSL
393
394
395
396
397#define CONFIG_ENV_OVERWRITE
398#ifndef CONFIG_KM_DEF_ENV
399#define CONFIG_KM_DEF_ENV "km-common=empty\0"
400#endif
401
402#ifndef MTDIDS_DEFAULT
403# define MTDIDS_DEFAULT "nand0=fsl_elbc_nand"
404#endif
405
406#ifndef MTDPARTS_DEFAULT
407# define MTDPARTS_DEFAULT "mtdparts=" \
408 "fsl_elbc_nand:" \
409 "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"
410#endif
411
412
413#define CONFIG_KM_DEF_BOOT_ARGS_CPU ""
414
415
416#define CONFIG_KM_DEF_ENV_CPU \
417 "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \
418 "cramfsloadfdt=" \
419 "cramfsload ${fdt_addr_r} " \
420 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
421 "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \
422 "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.pbl\0" \
423 "update=" \
424 "sf probe 0;sf erase 0 +${filesize};" \
425 "sf write ${load_addr_r} 0 ${filesize};\0" \
426 "set_fdthigh=true\0" \
427 "checkfdt=true\0" \
428 ""
429
430#define CONFIG_HW_ENV_SETTINGS \
431 "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \
432 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
433 "usb_dr_mode=host\0"
434
435#define CONFIG_KM_NEW_ENV \
436 "newenv=sf probe 0;" \
437 "sf erase " __stringify(CONFIG_ENV_OFFSET) " " \
438 __stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
439
440
441#ifndef CONFIG_KM_DEF_ARCH
442#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
443#endif
444
445#define CONFIG_EXTRA_ENV_SETTINGS \
446 CONFIG_KM_DEF_ENV \
447 CONFIG_KM_DEF_ARCH \
448 CONFIG_KM_NEW_ENV \
449 CONFIG_HW_ENV_SETTINGS \
450 "EEprom_ivm=pca9547:70:9\0" \
451 ""
452
453#endif
454