LXR uboot/arch/arm/cpu/armv8/fsl-layerscape/ls1046a

   1/*
   2 * Copyright 2016 Freescale Semiconductor, Inc.
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#include <common.h>
   8#include <asm/arch/fsl_serdes.h>
   9#include <asm/arch/immap_lsch2.h>
  10
  11struct serdes_config {
  12        u32 protocol;
  13        u8 lanes[SRDS_MAX_LANES];
  14};
  15
  16static struct serdes_config serdes1_cfg_tbl[] = {
  17        /* SerDes 1 */
  18        {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5,
  19                  SGMII_FM1_DTSEC6} },
  20        {0x1133, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC5,
  21                  SGMII_FM1_DTSEC6} },
  22        {0x1333, {XFI_FM1_MAC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5,
  23                  SGMII_FM1_DTSEC6} },
  24        {0x2333, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5,
  25                  SGMII_FM1_DTSEC6} },
  26        {0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10,
  27                  SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
  28        {0x1040, {XFI_FM1_MAC9, NONE, QSGMII_FM1_A, NONE} },
  29        {0x2040, {SGMII_2500_FM1_DTSEC9, NONE, QSGMII_FM1_A, NONE} },
  30        {0x1163, {XFI_FM1_MAC9, XFI_FM1_MAC10, PCIE1, SGMII_FM1_DTSEC6} },
  31        {0x2263, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, PCIE1,
  32                  SGMII_FM1_DTSEC6} },
  33        {0x3363, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, PCIE1,
  34                  SGMII_FM1_DTSEC6} },
  35        {0x2223, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10,
  36                  SGMII_2500_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
  37        {}
  38};
  39
  40static struct serdes_config serdes2_cfg_tbl[] = {
  41        /* SerDes 2 */
  42        {0x8888, {PCIE1, PCIE1, PCIE1, PCIE1} },
  43        {0x5559, {PCIE1, PCIE2, PCIE3, SATA1} },
  44        {0x5577, {PCIE1, PCIE2, PCIE3, PCIE3} },
  45        {0x5506, {PCIE1, PCIE2, NONE, PCIE3} },
  46        {0x0506, {NONE, PCIE2, NONE, PCIE3} },
  47        {0x0559, {NONE, PCIE2, PCIE3, SATA1} },
  48        {0x5A59, {PCIE1, SGMII_FM1_DTSEC2, PCIE3, SATA1} },
  49        {0x5A06, {PCIE1, SGMII_FM1_DTSEC2, NONE, PCIE3} },
  50        {}
  51};
  52
  53static struct serdes_config *serdes_cfg_tbl[] = {
  54        serdes1_cfg_tbl,
  55        serdes2_cfg_tbl,
  56};
  57
  58enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
  59{
  60        struct serdes_config *ptr;
  61
  62        if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
  63                return 0;
  64
  65        ptr = serdes_cfg_tbl[serdes];
  66        while (ptr->protocol) {
  67                if (ptr->protocol == cfg)
  68                        return ptr->lanes[lane];
  69                ptr++;
  70        }
  71
  72        return 0;
  73}
  74
  75int is_serdes_prtcl_valid(int serdes, u32 prtcl)
  76{
  77        int i;
  78        struct serdes_config *ptr;
  79
  80        if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
  81                return 0;
  82
  83        ptr = serdes_cfg_tbl[serdes];
  84        while (ptr->protocol) {
  85                if (ptr->protocol == prtcl)
  86                        break;
  87                ptr++;
  88        }
  89
  90        if (!ptr->protocol)
  91                return 0;
  92
  93        for (i = 0; i < SRDS_MAX_LANES; i++) {
  94                if (ptr->lanes[i] != NONE)
  95                        return 1;
  96        }
  97
  98        return 0;
  99}
 100