uboot/arch/arm/include/asm/arch-stv0991/stv0991_creg.h
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   1/*
   2 * (C) Copyright 2014
   3 * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8#ifndef _STV0991_CREG_H
   9#define _STV0991_CREG_H
  10
  11struct stv0991_creg {
  12        u32 version;            /* offset 0x0 */
  13        u32 hdpctl;             /* offset 0x4 */
  14        u32 hdpval;             /* offset 0x8 */
  15        u32 hdpgposet;          /* offset 0xc */
  16        u32 hdpgpoclr;          /* offset 0x10 */
  17        u32 hdpgpoval;          /* offset 0x14 */
  18        u32 stm_mux;            /* offset 0x18 */
  19        u32 sysctrl_1;          /* offset 0x1c */
  20        u32 sysctrl_2;          /* offset 0x20 */
  21        u32 sysctrl_3;          /* offset 0x24 */
  22        u32 sysctrl_4;          /* offset 0x28 */
  23        u32 reserved_1[0x35];   /* offset 0x2C-0xFC */
  24        u32 mux1;               /* offset 0x100 */
  25        u32 mux2;               /* offset 0x104 */
  26        u32 mux3;               /* offset 0x108 */
  27        u32 mux4;               /* offset 0x10c */
  28        u32 mux5;               /* offset 0x110 */
  29        u32 mux6;               /* offset 0x114 */
  30        u32 mux7;               /* offset 0x118 */
  31        u32 mux8;               /* offset 0x11c */
  32        u32 mux9;               /* offset 0x120 */
  33        u32 mux10;              /* offset 0x124 */
  34        u32 mux11;              /* offset 0x128 */
  35        u32 mux12;              /* offset 0x12c */
  36        u32 mux13;              /* offset 0x130 */
  37        u32 reserved_2[0x33];   /* offset 0x134-0x1FC */
  38        u32 cfg_pad1;           /* offset 0x200 */
  39        u32 cfg_pad2;           /* offset 0x204 */
  40        u32 cfg_pad3;           /* offset 0x208 */
  41        u32 cfg_pad4;           /* offset 0x20c */
  42        u32 cfg_pad5;           /* offset 0x210 */
  43        u32 cfg_pad6;           /* offset 0x214 */
  44        u32 cfg_pad7;           /* offset 0x218 */
  45        u32 reserved_3[0x39];   /* offset 0x21C-0x2FC */
  46        u32 vdd_pad1;           /* offset 0x300 */
  47        u32 vdd_pad2;           /* offset 0x304 */
  48        u32 reserved_4[0x3e];   /* offset 0x308-0x3FC */
  49        u32 vdd_comp1;          /* offset 0x400 */
  50};
  51
  52/* CREG MUX 13 register */
  53#define FLASH_CS_NC_SHIFT       4
  54#define FLASH_CS_NC_MASK        ~(7 << FLASH_CS_NC_SHIFT)
  55#define CFG_FLASH_CS_NC         (0 << FLASH_CS_NC_SHIFT)
  56
  57#define FLASH_CLK_SHIFT         0
  58#define FLASH_CLK_MASK          ~(7 << FLASH_CLK_SHIFT)
  59#define CFG_FLASH_CLK           (0 << FLASH_CLK_SHIFT)
  60
  61/* CREG MUX 12 register */
  62#define GPIOC_30_MUX_SHIFT      24
  63#define GPIOC_30_MUX_MASK       ~(1 << GPIOC_30_MUX_SHIFT)
  64#define CFG_GPIOC_30_UART_TX    (1 << GPIOC_30_MUX_SHIFT)
  65
  66#define GPIOC_31_MUX_SHIFT      28
  67#define GPIOC_31_MUX_MASK       ~(1 << GPIOC_31_MUX_SHIFT)
  68#define CFG_GPIOC_31_UART_RX    (1 << GPIOC_31_MUX_SHIFT)
  69
  70/* CREG MUX 7 register */
  71#define GPIOB_16_MUX_SHIFT      0
  72#define GPIOB_16_MUX_MASK       ~(1 << GPIOB_16_MUX_SHIFT)
  73#define CFG_GPIOB_16_UART_TX    (1 << GPIOB_16_MUX_SHIFT)
  74
  75#define GPIOB_17_MUX_SHIFT      4
  76#define GPIOB_17_MUX_MASK       ~(1 << GPIOB_17_MUX_SHIFT)
  77#define CFG_GPIOB_17_UART_RX    (1 << GPIOB_17_MUX_SHIFT)
  78
  79/* CREG CFG_PAD6 register */
  80
  81#define GPIOC_31_MODE_SHIFT     30
  82#define GPIOC_31_MODE_MASK      ~(1 << GPIOC_31_MODE_SHIFT)
  83#define CFG_GPIOC_31_MODE_OD    (0 << GPIOC_31_MODE_SHIFT)
  84#define CFG_GPIOC_31_MODE_PP    (1 << GPIOC_31_MODE_SHIFT)
  85
  86#define GPIOC_30_MODE_SHIFT     28
  87#define GPIOC_30_MODE_MASK      ~(1 << GPIOC_30_MODE_SHIFT)
  88#define CFG_GPIOC_30_MODE_LOW   (0 << GPIOC_30_MODE_SHIFT)
  89#define CFG_GPIOC_30_MODE_HIGH  (1 << GPIOC_30_MODE_SHIFT)
  90
  91/* CREG Ethernet pad config */
  92
  93#define VDD_ETH_PS_1V8          0
  94#define VDD_ETH_PS_2V5          2
  95#define VDD_ETH_PS_3V3          3
  96#define VDD_ETH_PS_MASK         0x3
  97
  98#define VDD_ETH_PS_SHIFT        12
  99#define ETH_VDD_CFG             (VDD_ETH_PS_1V8 << VDD_ETH_PS_SHIFT)
 100
 101#define VDD_ETH_M_PS_SHIFT      28
 102#define ETH_M_VDD_CFG           (VDD_ETH_PS_1V8 << VDD_ETH_M_PS_SHIFT)
 103
 104#endif
 105