LXR uboot/arch/arm/lib/cache-cp15.c

   1/*
   2 * (C) Copyright 2002
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8#include <common.h>
   9#include <asm/system.h>
  10#include <asm/cache.h>
  11#include <linux/compiler.h>
  12
  13#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
  14
  15DECLARE_GLOBAL_DATA_PTR;
  16
  17__weak void arm_init_before_mmu(void)
  18{
  19}
  20
  21__weak void arm_init_domains(void)
  22{
  23}
  24
  25static void cp_delay (void)
  26{
  27        volatile int i;
  28
  29        /* copro seems to need some delay between reading and writing */
  30        for (i = 0; i < 100; i++)
  31                nop();
  32        asm volatile("" : : : "memory");
  33}
  34
  35void set_section_dcache(int section, enum dcache_option option)
  36{
  37#ifdef CONFIG_ARMV7_LPAE
  38        u64 *page_table = (u64 *)gd->arch.tlb_addr;
  39        /* Need to set the access flag to not fault */
  40        u64 value = TTB_SECT_AP | TTB_SECT_AF;
  41#else
  42        u32 *page_table = (u32 *)gd->arch.tlb_addr;
  43        u32 value = TTB_SECT_AP;
  44#endif
  45
  46        /* Add the page offset */
  47        value |= ((u32)section << MMU_SECTION_SHIFT);
  48
  49        /* Add caching bits */
  50        value |= option;
  51
  52        /* Set PTE */
  53        page_table[section] = value;
  54}
  55
  56__weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
  57{
  58        debug("%s: Warning: not implemented\n", __func__);
  59}
  60
  61void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
  62                                     enum dcache_option option)
  63{
  64#ifdef CONFIG_ARMV7_LPAE
  65        u64 *page_table = (u64 *)gd->arch.tlb_addr;
  66#else
  67        u32 *page_table = (u32 *)gd->arch.tlb_addr;
  68#endif
  69        unsigned long startpt, stoppt;
  70        unsigned long upto, end;
  71
  72        end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
  73        start = start >> MMU_SECTION_SHIFT;
  74#ifdef CONFIG_ARMV7_LPAE
  75        debug("%s: start=%pa, size=%zu, option=%llx\n", __func__, &start, size,
  76              option);
  77#else
  78        debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size,
  79              option);
  80#endif
  81        for (upto = start; upto < end; upto++)
  82                set_section_dcache(upto, option);
  83
  84        /*
  85         * Make sure range is cache line aligned
  86         * Only CPU maintains page tables, hence it is safe to always
  87         * flush complete cache lines...
  88         */
  89
  90        startpt = (unsigned long)&page_table[start];
  91        startpt &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
  92        stoppt = (unsigned long)&page_table[end];
  93        stoppt = ALIGN(stoppt, CONFIG_SYS_CACHELINE_SIZE);
  94        mmu_page_table_flush(startpt, stoppt);
  95}
  96
  97__weak void dram_bank_mmu_setup(int bank)
  98{
  99        bd_t *bd = gd->bd;
 100        int     i;
 101
 102        debug("%s: bank: %d\n", __func__, bank);
 103        for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
 104             i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) +
 105                 (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT);
 106             i++) {
 107#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
 108                set_section_dcache(i, DCACHE_WRITETHROUGH);
 109#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
 110                set_section_dcache(i, DCACHE_WRITEALLOC);
 111#else
 112                set_section_dcache(i, DCACHE_WRITEBACK);
 113#endif
 114        }
 115}
 116
 117/* to activate the MMU we need to set up virtual memory: use 1M areas */
 118static inline void mmu_setup(void)
 119{
 120        int i;
 121        u32 reg;
 122
 123        arm_init_before_mmu();
 124        /* Set up an identity-mapping for all 4GB, rw for everyone */
 125        for (i = 0; i < ((4096ULL * 1024 * 1024) >> MMU_SECTION_SHIFT); i++)
 126                set_section_dcache(i, DCACHE_OFF);
 127
 128        for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 129                dram_bank_mmu_setup(i);
 130        }
 131
 132#ifdef CONFIG_ARMV7_LPAE
 133        /* Set up 4 PTE entries pointing to our 4 1GB page tables */
 134        for (i = 0; i < 4; i++) {
 135                u64 *page_table = (u64 *)(gd->arch.tlb_addr + (4096 * 4));
 136                u64 tpt = gd->arch.tlb_addr + (4096 * i);
 137                page_table[i] = tpt | TTB_PAGETABLE;
 138        }
 139
 140        reg = TTBCR_EAE;
 141#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
 142        reg |= TTBCR_ORGN0_WT | TTBCR_IRGN0_WT;
 143#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
 144        reg |= TTBCR_ORGN0_WBWA | TTBCR_IRGN0_WBWA;
 145#else
 146        reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA;
 147#endif
 148
 149        if (is_hyp()) {
 150                /* Set HCTR to enable LPAE */
 151                asm volatile("mcr p15, 4, %0, c2, c0, 2"
 152                        : : "r" (reg) : "memory");
 153                /* Set HTTBR0 */
 154                asm volatile("mcrr p15, 4, %0, %1, c2"
 155                        :
 156                        : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0)
 157                        : "memory");
 158                /* Set HMAIR */
 159                asm volatile("mcr p15, 4, %0, c10, c2, 0"
 160                        : : "r" (MEMORY_ATTRIBUTES) : "memory");
 161        } else {
 162                /* Set TTBCR to enable LPAE */
 163                asm volatile("mcr p15, 0, %0, c2, c0, 2"
 164                        : : "r" (reg) : "memory");
 165                /* Set 64-bit TTBR0 */
 166                asm volatile("mcrr p15, 0, %0, %1, c2"
 167                        :
 168                        : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0)
 169                        : "memory");
 170                /* Set MAIR */
 171                asm volatile("mcr p15, 0, %0, c10, c2, 0"
 172                        : : "r" (MEMORY_ATTRIBUTES) : "memory");
 173        }
 174#elif defined(CONFIG_CPU_V7)
 175        /* Set TTBR0 */
 176        reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK;
 177#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
 178        reg |= TTBR0_RGN_WT | TTBR0_IRGN_WT;
 179#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
 180        reg |= TTBR0_RGN_WBWA | TTBR0_IRGN_WBWA;
 181#else
 182        reg |= TTBR0_RGN_WB | TTBR0_IRGN_WB;
 183#endif
 184        asm volatile("mcr p15, 0, %0, c2, c0, 0"
 185                     : : "r" (reg) : "memory");
 186#else
 187        /* Copy the page table address to cp15 */
 188        asm volatile("mcr p15, 0, %0, c2, c0, 0"
 189                     : : "r" (gd->arch.tlb_addr) : "memory");
 190#endif
 191        /* Set the access control to all-supervisor */
 192        asm volatile("mcr p15, 0, %0, c3, c0, 0"
 193                     : : "r" (~0));
 194
 195        arm_init_domains();
 196
 197        /* and enable the mmu */
 198        reg = get_cr(); /* get control reg. */
 199        cp_delay();
 200        set_cr(reg | CR_M);
 201}
 202
 203static int mmu_enabled(void)
 204{
 205        return get_cr() & CR_M;
 206}
 207
 208/* cache_bit must be either CR_I or CR_C */
 209static void cache_enable(uint32_t cache_bit)
 210{
 211        uint32_t reg;
 212
 213        /* The data cache is not active unless the mmu is enabled too */
 214        if ((cache_bit == CR_C) && !mmu_enabled())
 215                mmu_setup();
 216        reg = get_cr(); /* get control reg. */
 217        cp_delay();
 218        set_cr(reg | cache_bit);
 219}
 220
 221/* cache_bit must be either CR_I or CR_C */
 222static void cache_disable(uint32_t cache_bit)
 223{
 224        uint32_t reg;
 225
 226        reg = get_cr();
 227        cp_delay();
 228
 229        if (cache_bit == CR_C) {
 230                /* if cache isn;t enabled no need to disable */
 231                if ((reg & CR_C) != CR_C)
 232                        return;
 233                /* if disabling data cache, disable mmu too */
 234                cache_bit |= CR_M;
 235        }
 236        reg = get_cr();
 237        cp_delay();
 238        if (cache_bit == (CR_C | CR_M))
 239                flush_dcache_all();
 240        set_cr(reg & ~cache_bit);
 241}
 242#endif
 243
 244#ifdef CONFIG_SYS_ICACHE_OFF
 245void icache_enable (void)
 246{
 247        return;
 248}
 249
 250void icache_disable (void)
 251{
 252        return;
 253}
 254
 255int icache_status (void)
 256{
 257        return 0;                                       /* always off */
 258}
 259#else
 260void icache_enable(void)
 261{
 262        cache_enable(CR_I);
 263}
 264
 265void icache_disable(void)
 266{
 267        cache_disable(CR_I);
 268}
 269
 270int icache_status(void)
 271{
 272        return (get_cr() & CR_I) != 0;
 273}
 274#endif
 275
 276#ifdef CONFIG_SYS_DCACHE_OFF
 277void dcache_enable (void)
 278{
 279        return;
 280}
 281
 282void dcache_disable (void)
 283{
 284        return;
 285}
 286
 287int dcache_status (void)
 288{
 289        return 0;                                       /* always off */
 290}
 291#else
 292void dcache_enable(void)
 293{
 294        cache_enable(CR_C);
 295}
 296
 297void dcache_disable(void)
 298{
 299        cache_disable(CR_C);
 300}
 301
 302int dcache_status(void)
 303{
 304        return (get_cr() & CR_C) != 0;
 305}
 306#endif
 307