LXR uboot/arch/mips/mach-ath79/ar933x/ddr.c

   1/*
   2 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
   3 * Based on Atheros LSDK/QSDK
   4 *
   5 * SPDX-License-Identifier: GPL-2.0+
   6 */
   7
   8#include <common.h>
   9#include <asm/io.h>
  10#include <asm/addrspace.h>
  11#include <asm/types.h>
  12#include <mach/ar71xx_regs.h>
  13#include <mach/ath79.h>
  14
  15DECLARE_GLOBAL_DATA_PTR;
  16
  17#define DDR_CTRL_UPD_EMR3S      BIT(5)
  18#define DDR_CTRL_UPD_EMR2S      BIT(4)
  19#define DDR_CTRL_PRECHARGE      BIT(3)
  20#define DDR_CTRL_AUTO_REFRESH   BIT(2)
  21#define DDR_CTRL_UPD_EMRS       BIT(1)
  22#define DDR_CTRL_UPD_MRS        BIT(0)
  23
  24#define DDR_REFRESH_EN          BIT(14)
  25#define DDR_REFRESH_M           0x3ff
  26#define DDR_REFRESH(x)          ((x) & 0x3ff)
  27#define DDR_REFRESH_VAL_25M     (DDR_REFRESH_EN | DDR_REFRESH(390))
  28#define DDR_REFRESH_VAL_40M     (DDR_REFRESH_EN | DDR_REFRESH(624))
  29
  30#define DDR_TRAS_S              0
  31#define DDR_TRAS_M              0x1f
  32#define DDR_TRAS(x)             ((x) << DDR_TRAS_S)
  33#define DDR_TRCD_M              0xf
  34#define DDR_TRCD_S              5
  35#define DDR_TRCD(x)             ((x) << DDR_TRCD_S)
  36#define DDR_TRP_M               0xf
  37#define DDR_TRP_S               9
  38#define DDR_TRP(x)              ((x) << DDR_TRP_S)
  39#define DDR_TRRD_M              0xf
  40#define DDR_TRRD_S              13
  41#define DDR_TRRD(x)             ((x) << DDR_TRRD_S)
  42#define DDR_TRFC_M              0x7f
  43#define DDR_TRFC_S              17
  44#define DDR_TRFC(x)             ((x) << DDR_TRFC_S)
  45#define DDR_TMRD_M              0xf
  46#define DDR_TMRD_S              23
  47#define DDR_TMRD(x)             ((x) << DDR_TMRD_S)
  48#define DDR_CAS_L_M             0x17
  49#define DDR_CAS_L_S             27
  50#define DDR_CAS_L(x)            (((x) & DDR_CAS_L_M) << DDR_CAS_L_S)
  51#define DDR_OPEN                BIT(30)
  52#define DDR_CONF_REG_VAL        (DDR_TRAS(16) | DDR_TRCD(6) | \
  53                                 DDR_TRP(6) | DDR_TRRD(4) | \
  54                                 DDR_TRFC(30) | DDR_TMRD(15) | \
  55                                 DDR_CAS_L(7) | DDR_OPEN)
  56
  57#define DDR_BURST_LEN_S         0
  58#define DDR_BURST_LEN_M         0xf
  59#define DDR_BURST_LEN(x)        ((x) << DDR_BURST_LEN_S)
  60#define DDR_BURST_TYPE          BIT(4)
  61#define DDR_CNTL_OE_EN          BIT(5)
  62#define DDR_PHASE_SEL           BIT(6)
  63#define DDR_CKE                 BIT(7)
  64#define DDR_TWR_S               8
  65#define DDR_TWR_M               0xf
  66#define DDR_TWR(x)              ((x) << DDR_TWR_S)
  67#define DDR_TRTW_S              12
  68#define DDR_TRTW_M              0x1f
  69#define DDR_TRTW(x)             ((x) << DDR_TRTW_S)
  70#define DDR_TRTP_S              17
  71#define DDR_TRTP_M              0xf
  72#define DDR_TRTP(x)             ((x) << DDR_TRTP_S)
  73#define DDR_TWTR_S              21
  74#define DDR_TWTR_M              0x1f
  75#define DDR_TWTR(x)             ((x) << DDR_TWTR_S)
  76#define DDR_G_OPEN_L_S          26
  77#define DDR_G_OPEN_L_M          0xf
  78#define DDR_G_OPEN_L(x)         ((x) << DDR_G_OPEN_L_S)
  79#define DDR_HALF_WIDTH_LOW      BIT(31)
  80#define DDR_CONF2_REG_VAL       (DDR_BURST_LEN(8) | DDR_CNTL_OE_EN | \
  81                                 DDR_CKE | DDR_TWR(6) | DDR_TRTW(14) | \
  82                                 DDR_TRTP(8) | DDR_TWTR(14) | \
  83                                 DDR_G_OPEN_L(7) | DDR_HALF_WIDTH_LOW)
  84
  85#define DDR2_CONF_TWL_S         10
  86#define DDR2_CONF_TWL_M         0xf
  87#define DDR2_CONF_TWL(x)        (((x) & DDR2_CONF_TWL_M) << DDR2_CONF_TWL_S)
  88#define DDR2_CONF_ODT           BIT(9)
  89#define DDR2_CONF_TFAW_S        2
  90#define DDR2_CONF_TFAW_M        0x3f
  91#define DDR2_CONF_TFAW(x)       (((x) & DDR2_CONF_TFAW_M) << DDR2_CONF_TFAW_S)
  92#define DDR2_CONF_EN            BIT(0)
  93#define DDR2_CONF_VAL           (DDR2_CONF_TWL(2) | DDR2_CONF_ODT | \
  94                                 DDR2_CONF_TFAW(22) | DDR2_CONF_EN)
  95
  96#define DDR1_EXT_MODE_VAL       0x02
  97#define DDR2_EXT_MODE_VAL       0x402
  98#define DDR2_EXT_MODE_OCD_VAL   0x382
  99#define DDR1_MODE_DLL_VAL       0x133
 100#define DDR2_MODE_DLL_VAL       0x100
 101#define DDR1_MODE_VAL           0x33
 102#define DDR2_MODE_VAL           0xa33
 103#define DDR_TAP_VAL0            0x08
 104#define DDR_TAP_VAL1            0x09
 105
 106void ddr_init(void)
 107{
 108        void __iomem *regs;
 109        u32 val;
 110
 111        regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
 112                           MAP_NOCACHE);
 113
 114        writel(DDR_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
 115        writel(DDR_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
 116
 117        val = ath79_get_bootstrap();
 118        if (val & AR933X_BOOTSTRAP_DDR2) {
 119                /* AHB maximum timeout */
 120                writel(0xfffff, regs + AR933X_DDR_REG_TIMEOUT_MAX);
 121
 122                /* Enable DDR2 */
 123                writel(DDR2_CONF_VAL, regs + AR933X_DDR_REG_DDR2_CONFIG);
 124
 125                /* Precharge All */
 126                writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
 127
 128                /* Disable High Temperature Self-Refresh, Full Array */
 129                writel(0x00, regs + AR933X_DDR_REG_EMR2);
 130
 131                /* Extended Mode Register 2 Set (EMR2S) */
 132                writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL);
 133
 134                writel(0x00, regs + AR933X_DDR_REG_EMR3);
 135
 136                /* Extended Mode Register 3 Set (EMR3S) */
 137                writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL);
 138
 139                /* Enable DLL,  Full strength, ODT Disabled */
 140                writel(0x00, regs + AR71XX_DDR_REG_EMR);
 141
 142                /* Extended Mode Register Set (EMRS) */
 143                writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
 144
 145                /* Reset DLL */
 146                writel(DDR2_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
 147
 148                /* Mode Register Set (MRS) */
 149                writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
 150
 151                /* Precharge All */
 152                writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
 153
 154                /* Auto Refresh */
 155                writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
 156                writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
 157
 158                /* Write recovery (WR) 6 clock, CAS Latency 3, Burst Length 8 */
 159                writel(DDR2_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
 160                /* Mode Register Set (MRS) */
 161                writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
 162
 163                /* Enable OCD defaults, Enable DLL, Reduced Drive Strength */
 164                writel(DDR2_EXT_MODE_OCD_VAL, regs + AR71XX_DDR_REG_EMR);
 165
 166                /* Extended Mode Register Set (EMRS) */
 167                writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
 168
 169                /* OCD exit, Enable DLL, Enable /DQS, Reduced Drive Strength */
 170                writel(DDR2_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
 171                /* Extended Mode Register Set (EMRS) */
 172                writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
 173
 174                /* Refresh time control */
 175                if (val & AR933X_BOOTSTRAP_REF_CLK_40)
 176                        writel(DDR_REFRESH_VAL_40M, regs +
 177                               AR71XX_DDR_REG_REFRESH);
 178                else
 179                        writel(DDR_REFRESH_VAL_25M, regs +
 180                               AR71XX_DDR_REG_REFRESH);
 181
 182                /* DQS 0 Tap Control */
 183                writel(DDR_TAP_VAL0, regs + AR71XX_DDR_REG_TAP_CTRL0);
 184
 185                /* DQS 1 Tap Control */
 186                writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1);
 187
 188                /* For 16-bit DDR */
 189                writel(0xff, regs + AR71XX_DDR_REG_RD_CYCLE);
 190        } else {
 191                /* AHB maximum timeout */
 192                writel(0xfffff, regs + AR933X_DDR_REG_TIMEOUT_MAX);
 193
 194                /* Precharge All */
 195                writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
 196
 197                /* Reset DLL, Burst Length 8, CAS Latency 3 */
 198                writel(DDR1_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
 199
 200                /* Forces an MRS update cycle in DDR */
 201                writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
 202
 203                /* Enable DLL, Full strength */
 204                writel(DDR1_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
 205
 206                /* Extended Mode Register Set (EMRS) */
 207                writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
 208
 209                /* Precharge All */
 210                writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
 211
 212                /* Normal DLL, Burst Length 8, CAS Latency 3 */
 213                writel(DDR1_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
 214
 215                /* Mode Register Set (MRS) */
 216                writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
 217
 218                /* Refresh time control */
 219                if (val & AR933X_BOOTSTRAP_REF_CLK_40)
 220                        writel(DDR_REFRESH_VAL_40M, regs +
 221                               AR71XX_DDR_REG_REFRESH);
 222                else
 223                        writel(DDR_REFRESH_VAL_25M, regs +
 224                               AR71XX_DDR_REG_REFRESH);
 225
 226                /* DQS 0 Tap Control */
 227                writel(DDR_TAP_VAL0, regs + AR71XX_DDR_REG_TAP_CTRL0);
 228
 229                /* DQS 1 Tap Control */
 230                writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1);
 231
 232                /* For 16-bit DDR */
 233                writel(0xff, regs + AR71XX_DDR_REG_RD_CYCLE);
 234        }
 235}
 236
 237void ddr_tap_tuning(void)
 238{
 239        void __iomem *regs;
 240        u32 *addr_k0, *addr_k1, *addr;
 241        u32 val, tap, upper, lower;
 242        int i, j, dir, err, done;
 243
 244        regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
 245                           MAP_NOCACHE);
 246
 247        /* Init memory pattern */
 248        addr = (void *)CKSEG0ADDR(0x2000);
 249        for (i = 0; i < 256; i++) {
 250                val = 0;
 251                for (j = 0; j < 8; j++) {
 252                        if (i & (1 << j)) {
 253                                if (j % 2)
 254                                        val |= 0xffff0000;
 255                                else
 256                                        val |= 0x0000ffff;
 257                        }
 258
 259                        if (j % 2) {
 260                                *addr++ = val;
 261                                val = 0;
 262                        }
 263                }
 264        }
 265
 266        err = 0;
 267        done = 0;
 268        dir = 1;
 269        tap = readl(regs + AR71XX_DDR_REG_TAP_CTRL0);
 270        val = tap;
 271        upper = tap;
 272        lower = tap;
 273        while (!done) {
 274                err = 0;
 275
 276                /* Update new DDR tap value */
 277                writel(val, regs + AR71XX_DDR_REG_TAP_CTRL0);
 278                writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1);
 279
 280                /* Compare DDR with cache */
 281                for (i = 0; i < 2; i++) {
 282                        addr_k1 = (void *)CKSEG1ADDR(0x2000);
 283                        addr_k0 = (void *)CKSEG0ADDR(0x2000);
 284                        addr = (void *)CKSEG0ADDR(0x3000);
 285
 286                        while (addr_k0 < addr) {
 287                                if (*addr_k1++ != *addr_k0++) {
 288                                        err = 1;
 289                                        break;
 290                                }
 291                        }
 292
 293                        if (err)
 294                                break;
 295                }
 296
 297                if (err) {
 298                        /* Save upper/lower threshold if error  */
 299                        if (dir) {
 300                                dir = 0;
 301                                val--;
 302                                upper = val;
 303                                val = tap;
 304                        } else {
 305                                val++;
 306                                lower = val;
 307                                done = 1;
 308                        }
 309                } else {
 310                        /* Try the next value until limitation */
 311                        if (dir) {
 312                                if (val < 0x20) {
 313                                        val++;
 314                                } else {
 315                                        dir = 0;
 316                                        upper = val;
 317                                        val = tap;
 318                                }
 319                        } else {
 320                                if (!val) {
 321                                        lower = val;
 322                                        done = 1;
 323                                } else {
 324                                        val--;
 325                                }
 326                        }
 327                }
 328        }
 329
 330        /* compute an intermediate value and write back */
 331        val = (upper + lower) / 2;
 332        writel(val, regs + AR71XX_DDR_REG_TAP_CTRL0);
 333        val++;
 334        writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1);
 335}
 336