LXR uboot/arch/nds32/cpu/n1213/ag101/lowlevel

   1/*
   2 * Copyright (C) 2011 Andes Technology Corporation
   3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
   4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
   5 *
   6 * SPDX-License-Identifier:     GPL-2.0+
   7 */
   8
   9.pic
  10
  11.text
  12
  13#include <common.h>
  14#include <config.h>
  15
  16#include <asm/macro.h>
  17#include <generated/asm-offsets.h>
  18
  19/*
  20 * parameters for the SDRAM controller
  21 */
  22#define SDMC_TP1_A              (CONFIG_FTSDMC021_BASE + FTSDMC021_TP1)
  23#define SDMC_TP2_A              (CONFIG_FTSDMC021_BASE + FTSDMC021_TP2)
  24#define SDMC_CR1_A              (CONFIG_FTSDMC021_BASE + FTSDMC021_CR1)
  25#define SDMC_CR2_A              (CONFIG_FTSDMC021_BASE + FTSDMC021_CR2)
  26#define SDMC_B0_BSR_A           (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR)
  27#define SDMC_B1_BSR_A           (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK1_BSR)
  28
  29#define SDMC_TP1_D              CONFIG_SYS_FTSDMC021_TP1
  30#define SDMC_TP2_D              CONFIG_SYS_FTSDMC021_TP2
  31#define SDMC_CR1_D              CONFIG_SYS_FTSDMC021_CR1
  32#define SDMC_CR2_D              CONFIG_SYS_FTSDMC021_CR2
  33
  34#define SDMC_B0_BSR_D           CONFIG_SYS_FTSDMC021_BANK0_BSR
  35#define SDMC_B1_BSR_D           CONFIG_SYS_FTSDMC021_BANK1_BSR
  36
  37
  38/*
  39 * for Orca and Emerald
  40 */
  41#define BOARD_ID_REG            0x104
  42#define BOARD_ID_FAMILY_MASK    0xfff000
  43#define BOARD_ID_FAMILY_V5      0x556000
  44#define BOARD_ID_FAMILY_K7      0x74b000
  45
  46/*
  47 * parameters for the static memory controller
  48 */
  49#define SMC_BANK0_CR_A          (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR)
  50#define SMC_BANK0_TPR_A         (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR)
  51
  52#define SMC_BANK0_CR_D          FTSMC020_BANK0_LOWLV_CONFIG
  53#define SMC_BANK0_TPR_D         FTSMC020_BANK0_LOWLV_TIMING
  54
  55/*
  56 * parameters for the ahbc controller
  57 */
  58#define AHBC_CR_A               (CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
  59#define AHBC_BSR6_A     (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
  60
  61/*
  62 * for Orca and Emerald
  63 */
  64#define AHBC_BSR4_A     (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_4)
  65#define AHBC_BSR6_D             CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
  66
  67/*
  68 * parameters for the pmu controoler
  69 */
  70#define PMU_PDLLCR0_A           (CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
  71
  72/*
  73 * numeric 7 segment display
  74 */
  75.macro  led, num
  76        write32 CONFIG_DEBUG_LED, \num
  77.endm
  78
  79/*
  80 * Waiting for SDRAM to set up
  81 */
  82.macro  wait_sdram
  83        li      $r0, CONFIG_FTSDMC021_BASE
  841:
  85        lwi     $r1, [$r0+FTSDMC021_CR2]
  86        bnez    $r1, 1b
  87.endm
  88
  89#ifndef CONFIG_SKIP_LOWLEVEL_INIT
  90.globl  lowlevel_init
  91lowlevel_init:
  92        move    $r10, $lp
  93
  94        led     0x0
  95        jal     mem_init
  96
  97        led     0x10
  98        jal     remap
  99
 100#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
 101        led     0x1f
 102        jal     enable_fpu
 103#endif
 104
 105        led     0x20
 106        ret     $r10
 107
 108mem_init:
 109        move    $r11, $lp
 110
 111        /*
 112         * mem_init:
 113         *      There are 2 bank connected to FTSMC020 on AG101
 114         *      BANK0: FLASH/ROM (SW5, J16), BANK1: OnBoard SDRAM.
 115         *      we need to set onboard SDRAM before remap and relocation.
 116         */
 117        led     0x01
 118
 119  /*
 120   * for Orca and Emerald
 121   * disable write protection and reset bank size
 122   */
 123        li      $r0, SMC_BANK0_CR_A
 124        lwi $r1, [$r0+#0x00]
 125        ori $r1, $r1, 0x8f0
 126        xori $r1, $r1, 0x8f0
 127  /*
 128   * check board
 129   */
 130        li      $r3, CONFIG_FTPMU010_BASE + BOARD_ID_REG
 131  lwi     $r3, [$r3]
 132  li      $r4, BOARD_ID_FAMILY_MASK
 133  and     $r3, $r3, $r4
 134  li      $r4, BOARD_ID_FAMILY_K7
 135  xor     $r4, $r3, $r4
 136  beqz    $r4, use_flash_16bit_boot
 137  /*
 138   * 32-bit mode
 139   */
 140use_flash_32bit_boot:
 141        ori     $r1, $r1, 0x50
 142  li      $r2, 0x00151151
 143  j       sdram_b0_cr
 144  /*
 145   * 16-bit mode
 146   */
 147use_flash_16bit_boot:
 148  ori     $r1, $r1, 0x60
 149  li      $r2, 0x00153153
 150  /*
 151   * SRAM bank0 config
 152   */
 153sdram_b0_cr:
 154  swi     $r1, [$r0+#0x00]
 155  swi     $r2, [$r0+#0x04]
 156
 157        /*
 158         * config AHB Controller
 159         */
 160        led     0x02
 161
 162        /*
 163         * config PMU controller
 164         */
 165        /* ftpmu010_dlldis_disable, must do it in lowleve_init */
 166        led     0x03
 167        setbf32 PMU_PDLLCR0_A, FTPMU010_PDLLCR0_DLLDIS          ! 0x00010000
 168
 169        /*
 170         * config SDRAM controller
 171         */
 172        led     0x04
 173        write32 SDMC_TP1_A, SDMC_TP1_D                          ! 0x00011312
 174        led     0x05
 175        write32 SDMC_TP2_A, SDMC_TP2_D                          ! 0x00480180
 176        led     0x06
 177        write32 SDMC_CR1_A, SDMC_CR1_D                          ! 0x00002326
 178
 179        led     0x07
 180        write32 SDMC_CR2_A, FTSDMC021_CR2_IPREC                 ! 0x00000010
 181        wait_sdram
 182
 183        led     0x08
 184        write32 SDMC_CR2_A, FTSDMC021_CR2_ISMR                  ! 0x00000004
 185        wait_sdram
 186
 187        led     0x09
 188        write32 SDMC_CR2_A, FTSDMC021_CR2_IREF                  ! 0x00000008
 189        wait_sdram
 190
 191        led     0x0a
 192        move    $lp, $r11
 193        ret
 194
 195remap:
 196        move    $r11, $lp
 197#ifdef __NDS32_N1213_43U1H__    /* NDS32 V0 ISA - AG101 Only */
 198        bal     2f
 199relo_base:
 200        move    $r0, $lp
 201#else
 202relo_base:
 203        mfusr   $r0, $pc
 204#endif /* __NDS32_N1213_43U1H__ */
 205
 206        /*
 207         * Remapping
 208         */
 209        led     0x1a
 210        write32 SDMC_B0_BSR_A, SDMC_B0_BSR_D            ! 0x00001800
 211        write32 SDMC_B1_BSR_A, SDMC_B1_BSR_D            ! 0x00001880
 212
 213        /* clear empty BSR registers */
 214        led     0x1b
 215        li      $r4, CONFIG_FTSDMC021_BASE
 216        li      $r5, 0x0
 217        swi     $r5, [$r4 + FTSDMC021_BANK2_BSR]
 218        swi     $r5, [$r4 + FTSDMC021_BANK3_BSR]
 219
 220#ifdef CONFIG_MEM_REMAP
 221        /*
 222         * Copy ROM code to SDRAM base for memory remap layout.
 223         * This is not the real relocation, the real relocation is the function
 224         * relocate_code() is start.S which supports the systems is memory
 225         * remapped or not.
 226         */
 227        /*
 228         * Doing memory remap is essential for preparing some non-OS or RTOS
 229         * applications.
 230         *
 231         * This is also a must on ADP-AG101 board.
 232         * The reason is because the ROM/FLASH circuit on PCB board.
 233         * AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
 234         * ROM/FLASH is used to boot.
 235         *
 236         * When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
 237         * and the FLASH is connected to BANK1.
 238         * When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
 239         * and the FLASH is connected to BANK0.
 240         * It will occur problem when doing flash probing if the flash is at
 241         * BANK0 (0x00000000) while memory remapping was skipped.
 242         *
 243         * Other board like ADP-AG101P may not enable this since there is only
 244         * a FLASH connected to bank0.
 245         */
 246        led     0x11
 247   /*
 248    * for Orca and Emerald
 249    * read sdram base address automatically
 250    */
 251        li      $r5, AHBC_BSR6_A
 252        lwi $r8, [$r5]
 253        li      $r4, 0xfff00000   /* r4 = bank6 base */
 254        and $r4, $r4, $r8
 255
 256        la      $r5, _start@GOTOFF
 257        la  $r6, _end@GOTOFF
 2581:
 259        lwi.p   $r7, [$r5], #4
 260        swi.p   $r7, [$r4], #4
 261        blt     $r5, $r6, 1b
 262
 263        /* set remap bit */
 264        /*
 265         * MEM remap bit is operational
 266         * - use it to map writeable memory at 0x00000000, in place of flash
 267         * - before remap: flash/rom 0x00000000, sdram: 0x10000000-0x4fffffff
 268         * - after  remap: flash/rom 0x80000000, sdram: 0x00000000
 269         */
 270        led     0x1c
 271        write32 SDMC_B0_BSR_A, 0x00001000
 272        write32 SDMC_B1_BSR_A, 0x00001200
 273        li $r5, CONFIG_SYS_TEXT_BASE    /* flash base address */
 274        add $r11, $r11, $r5     /* add flash address offset for ret */
 275        add $r10, $r10, $r5
 276        move $lp, $r11
 277        setbf15 AHBC_CR_A, FTAHBC020S_CR_REMAP          ! 0x1
 278
 279  /*
 280   * for Orca and Emerald
 281   * extend sdram size from 256MB to 2GB
 282   */
 283        li      $r5, AHBC_BSR6_A
 284        lwi $r6, [$r5]
 285        li  $r4, 0xfff0ffff
 286        and $r6 ,$r4, $r6
 287        li      $r4, 0x000b0000
 288        or  $r6, $r4, $r6
 289        swi     $r6, [$r5]
 290
 291  /*
 292   * for Orca and Emerald
 293   * extend rom base from 256MB to 2GB
 294   */
 295        li      $r4, AHBC_BSR4_A
 296        lwi $r5, [$r4]
 297        li      $r6, 0xffffff
 298        and $r5, $r5, $r6
 299        li  $r6, 0x80000000
 300        or  $r5, $r5, $r6
 301        swi $r5,        [$r4]
 302#endif /* #ifdef CONFIG_MEM_REMAP */
 303        move $lp, $r11
 3042:
 305        ret
 306
 307        /*
 308         * enable_fpu:
 309         *  Some of Andes CPU version support FPU coprocessor, if so,
 310         *  and toolchain support FPU instruction set, we should enable it.
 311         */
 312#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
 313enable_fpu:
 314        mfsr    $r0, $CPU_VER     /* enable FPU if it exists */
 315        srli    $r0, $r0, 3
 316        andi    $r0, $r0, 1
 317        beqz    $r0, 1f           /* skip if no COP */
 318        mfsr    $r0, $FUCOP_EXIST
 319        srli    $r0, $r0, 31
 320        beqz    $r0, 1f           /* skip if no FPU */
 321        mfsr    $r0, $FUCOP_CTL
 322        ori     $r0, $r0, 1
 323        mtsr    $r0, $FUCOP_CTL
 3241:
 325        ret
 326#endif
 327
 328.globl show_led
 329show_led:
 330    li      $r8, (CONFIG_DEBUG_LED)
 331    swi     $r7, [$r8]
 332    ret
 333#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */
 334