LXR uboot/arch/powerpc/cpu/mpc8260/cpu

   1/*
   2 * (C) Copyright 2000-2002
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8#include <common.h>
   9#include <mpc8260.h>
  10#include <asm/cpm_8260.h>
  11#include <ioports.h>
  12
  13DECLARE_GLOBAL_DATA_PTR;
  14
  15#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
  16extern unsigned long board_get_cpu_clk_f (void);
  17#endif
  18
  19static void config_8260_ioports (volatile immap_t * immr)
  20{
  21        int portnum;
  22
  23        for (portnum = 0; portnum < 4; portnum++) {
  24                uint pmsk = 0,
  25                     ppar = 0,
  26                     psor = 0,
  27                     pdir = 0,
  28                     podr = 0,
  29                     pdat = 0;
  30                iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
  31                iop_conf_t *eiopc = iopc + 32;
  32                uint msk = 1;
  33
  34                /*
  35                 * NOTE:
  36                 * index 0 refers to pin 31,
  37                 * index 31 refers to pin 0
  38                 */
  39                while (iopc < eiopc) {
  40                        if (iopc->conf) {
  41                                pmsk |= msk;
  42                                if (iopc->ppar)
  43                                        ppar |= msk;
  44                                if (iopc->psor)
  45                                        psor |= msk;
  46                                if (iopc->pdir)
  47                                        pdir |= msk;
  48                                if (iopc->podr)
  49                                        podr |= msk;
  50                                if (iopc->pdat)
  51                                        pdat |= msk;
  52                        }
  53
  54                        msk <<= 1;
  55                        iopc++;
  56                }
  57
  58                if (pmsk != 0) {
  59                        volatile ioport_t *iop = ioport_addr (immr, portnum);
  60                        uint tpmsk = ~pmsk;
  61
  62                        /*
  63                         * the (somewhat confused) paragraph at the
  64                         * bottom of page 35-5 warns that there might
  65                         * be "unknown behaviour" when programming
  66                         * PSORx and PDIRx, if PPARx = 1, so I
  67                         * decided this meant I had to disable the
  68                         * dedicated function first, and enable it
  69                         * last.
  70                         */
  71                        iop->ppar &= tpmsk;
  72                        iop->psor = (iop->psor & tpmsk) | psor;
  73                        iop->podr = (iop->podr & tpmsk) | podr;
  74                        iop->pdat = (iop->pdat & tpmsk) | pdat;
  75                        iop->pdir = (iop->pdir & tpmsk) | pdir;
  76                        iop->ppar |= ppar;
  77                }
  78        }
  79}
  80
  81#define SET_VAL_MASK(a, b, mask) ((a & mask) | (b & ~mask))
  82/*
  83 * Breath some life into the CPU...
  84 *
  85 * Set up the memory map,
  86 * initialize a bunch of registers,
  87 * initialize the UPM's
  88 */
  89void cpu_init_f (volatile immap_t * immr)
  90{
  91        uint sccr;
  92#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
  93        unsigned long cpu_clk;
  94#endif
  95        volatile memctl8260_t *memctl = &immr->im_memctl;
  96        extern void m8260_cpm_reset (void);
  97
  98        /* Pointer is writable since we allocated a register for it */
  99        gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
 100
 101        /* Clear initial global data */
 102        memset ((void *) gd, 0, sizeof (gd_t));
 103
 104        /* RSR - Reset Status Register - clear all status (5-4) */
 105        gd->arch.reset_status = immr->im_clkrst.car_rsr;
 106        immr->im_clkrst.car_rsr = RSR_ALLBITS;
 107
 108        /* RMR - Reset Mode Register - contains checkstop reset enable (5-5) */
 109        immr->im_clkrst.car_rmr = CONFIG_SYS_RMR;
 110
 111        /* BCR - Bus Configuration Register (4-25) */
 112#if defined(CONFIG_SYS_BCR_60x) && (CONFIG_SYS_BCR_SINGLE)
 113        if (immr->im_siu_conf.sc_bcr & BCR_EBM) {
 114                immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CONFIG_SYS_BCR_60x, 0x80000010);
 115        } else {
 116                immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CONFIG_SYS_BCR_SINGLE, 0x80000010);
 117        }
 118#else
 119        immr->im_siu_conf.sc_bcr = CONFIG_SYS_BCR;
 120#endif
 121
 122        /* SIUMCR - contains debug pin configuration (4-31) */
 123#if defined(CONFIG_SYS_SIUMCR_LOW) && (CONFIG_SYS_SIUMCR_HIGH)
 124        cpu_clk = board_get_cpu_clk_f ();
 125        if (cpu_clk >= 100000000) {
 126                immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR_HIGH, 0x9f3cc000);
 127        } else {
 128                immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR_LOW, 0x9f3cc000);
 129        }
 130#else
 131        immr->im_siu_conf.sc_siumcr = CONFIG_SYS_SIUMCR;
 132#endif
 133
 134        config_8260_ioports (immr);
 135
 136        /* initialize time counter status and control register (4-40) */
 137        immr->im_sit.sit_tmcntsc = CONFIG_SYS_TMCNTSC;
 138
 139        /* initialize the PIT (4-42) */
 140        immr->im_sit.sit_piscr = CONFIG_SYS_PISCR;
 141
 142        /* System clock control register (9-8) */
 143        sccr = immr->im_clkrst.car_sccr &
 144                (SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK);
 145        immr->im_clkrst.car_sccr = sccr |
 146                (CONFIG_SYS_SCCR & ~(SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK) );
 147
 148        /*
 149         * Memory Controller:
 150         */
 151
 152        /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
 153         * addresses - these have to be modified later when FLASH size
 154         * has been determined
 155         */
 156
 157#if defined(CONFIG_SYS_OR0_REMAP)
 158        memctl->memc_or0 = CONFIG_SYS_OR0_REMAP;
 159#endif
 160#if defined(CONFIG_SYS_OR1_REMAP)
 161        memctl->memc_or1 = CONFIG_SYS_OR1_REMAP;
 162#endif
 163
 164        /* now restrict to preliminary range */
 165        /* the PS came from the HRCW, don't change it */
 166        memctl->memc_br0 = SET_VAL_MASK(memctl->memc_br0 , CONFIG_SYS_BR0_PRELIM, BRx_PS_MSK);
 167        memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM;
 168
 169#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
 170        memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
 171        memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
 172#endif
 173
 174#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
 175        memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
 176        memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
 177#endif
 178
 179#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
 180        memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
 181        memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
 182#endif
 183
 184#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
 185        memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
 186        memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
 187#endif
 188
 189#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
 190        memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM;
 191        memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM;
 192#endif
 193
 194#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
 195        memctl->memc_or6 = CONFIG_SYS_OR6_PRELIM;
 196        memctl->memc_br6 = CONFIG_SYS_BR6_PRELIM;
 197#endif
 198
 199#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
 200        memctl->memc_or7 = CONFIG_SYS_OR7_PRELIM;
 201        memctl->memc_br7 = CONFIG_SYS_BR7_PRELIM;
 202#endif
 203
 204#if defined(CONFIG_SYS_BR8_PRELIM) && defined(CONFIG_SYS_OR8_PRELIM)
 205        memctl->memc_or8 = CONFIG_SYS_OR8_PRELIM;
 206        memctl->memc_br8 = CONFIG_SYS_BR8_PRELIM;
 207#endif
 208
 209#if defined(CONFIG_SYS_BR9_PRELIM) && defined(CONFIG_SYS_OR9_PRELIM)
 210        memctl->memc_or9 = CONFIG_SYS_OR9_PRELIM;
 211        memctl->memc_br9 = CONFIG_SYS_BR9_PRELIM;
 212#endif
 213
 214#if defined(CONFIG_SYS_BR10_PRELIM) && defined(CONFIG_SYS_OR10_PRELIM)
 215        memctl->memc_or10 = CONFIG_SYS_OR10_PRELIM;
 216        memctl->memc_br10 = CONFIG_SYS_BR10_PRELIM;
 217#endif
 218
 219#if defined(CONFIG_SYS_BR11_PRELIM) && defined(CONFIG_SYS_OR11_PRELIM)
 220        memctl->memc_or11 = CONFIG_SYS_OR11_PRELIM;
 221        memctl->memc_br11 = CONFIG_SYS_BR11_PRELIM;
 222#endif
 223
 224        m8260_cpm_reset ();
 225}
 226
 227/*
 228 * initialize higher level parts of CPU like time base and timers
 229 */
 230int cpu_init_r (void)
 231{
 232        volatile immap_t *immr = (immap_t *) gd->bd->bi_immr_base;
 233
 234        immr->im_cpm.cp_rccr = CONFIG_SYS_RCCR;
 235
 236        return (0);
 237}
 238
 239/*
 240 * print out the reason for the reset
 241 */
 242int prt_8260_rsr (void)
 243{
 244        static struct {
 245                ulong mask;
 246                char *desc;
 247        } bits[] = {
 248                {
 249                RSR_JTRS, "JTAG"}, {
 250                RSR_CSRS, "Check Stop"}, {
 251                RSR_SWRS, "Software Watchdog"}, {
 252                RSR_BMRS, "Bus Monitor"}, {
 253                RSR_ESRS, "External Soft"}, {
 254                RSR_EHRS, "External Hard"}
 255        };
 256        static int n = ARRAY_SIZE(bits);
 257        ulong rsr = gd->arch.reset_status;
 258        int i;
 259        char *sep;
 260
 261        puts (CPU_ID_STR " Reset Status:");
 262
 263        sep = " ";
 264        for (i = 0; i < n; i++)
 265                if (rsr & bits[i].mask) {
 266                        printf ("%s%s", sep, bits[i].desc);
 267                        sep = ", ";
 268                }
 269
 270        puts ("\n\n");
 271        return (0);
 272}
 273