LXR uboot/board/Synology/ds414/ds414.c

   1/*
   2 *
   3 * Copyright (C) 2015 Phil Sutter <phil@nwl.cc>
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8#include <common.h>
   9#include <miiphy.h>
  10#include <asm/io.h>
  11#include <asm/arch/cpu.h>
  12#include <asm/arch/soc.h>
  13#include <linux/mbus.h>
  14
  15#include "../drivers/ddr/marvell/axp/ddr3_hw_training.h"
  16#include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h"
  17#include "../arch/arm/mach-mvebu/serdes/axp/board_env_spec.h"
  18
  19DECLARE_GLOBAL_DATA_PTR;
  20
  21/* GPP and MPP settings as found in mvBoardEnvSpec.c of Synology's U-Boot */
  22
  23#define DS414_GPP_OUT_VAL_LOW           (BIT(25) | BIT(30))
  24#define DS414_GPP_OUT_VAL_MID           (BIT(10) | BIT(15))
  25#define DS414_GPP_OUT_VAL_HIGH          (0)
  26
  27#define DS414_GPP_OUT_POL_LOW           (0)
  28#define DS414_GPP_OUT_POL_MID           (0)
  29#define DS414_GPP_OUT_POL_HIGH          (0)
  30
  31#define DS414_GPP_OUT_ENA_LOW           (~(BIT(25) | BIT(30)))
  32#define DS414_GPP_OUT_ENA_MID           (~(BIT(10) | BIT(12) | \
  33                                           BIT(13) | BIT(14) | BIT(15)))
  34#define DS414_GPP_OUT_ENA_HIGH          (~0)
  35
  36static const u32 ds414_mpp_control[] = {
  37        0x11111111,
  38        0x22221111,
  39        0x22222222,
  40        0x00000000,
  41        0x11110000,
  42        0x00004000,
  43        0x00000000,
  44        0x00000000,
  45        0x00000000
  46};
  47
  48/* DDR3 static MC configuration */
  49
  50/* 1G_v1 (4x2Gbits) adapted by DS414 */
  51MV_DRAM_MC_INIT syno_ddr3_b0_667_1g_v1[MV_MAX_DDR3_STATIC_SIZE] = {
  52        {0x00001400, 0x73014A28},       /*DDR SDRAM Configuration Register */
  53        {0x00001404, 0x30000800},       /*Dunit Control Low Register */
  54        {0x00001408, 0x44148887},       /*DDR SDRAM Timing (Low) Register */
  55        {0x0000140C, 0x3AD83FEA},       /*DDR SDRAM Timing (High) Register */
  56
  57        {0x00001410, 0x14000000},       /*DDR SDRAM Address Control Register */
  58
  59        {0x00001414, 0x00000000},       /*DDR SDRAM Open Pages Control Register */
  60        {0x00001418, 0x00000e00},       /*DDR SDRAM Operation Register */
  61        {0x00001420, 0x00000004},       /*DDR SDRAM Extended Mode Register */
  62        {0x00001424, 0x0000F3FF},       /*Dunit Control High Register */
  63        {0x00001428, 0x000F8830},       /*Dunit Control High Register */
  64        {0x0000142C, 0x054C36F4},       /*Dunit Control High Register */
  65        {0x0000147C, 0x0000C671},
  66
  67        {0x000014a0, 0x00000001},
  68        {0x000014a8, 0x00000100},       /*2:1 */
  69        {0x00020220, 0x00000006},
  70
  71        {0x00001494, 0x00010000},       /*DDR SDRAM ODT Control (Low) Register */
  72        {0x00001498, 0x00000000},       /*DDR SDRAM ODT Control (High) Register */
  73        {0x0000149C, 0x00000001},       /*DDR Dunit ODT Control Register */
  74
  75        {0x000014C0, 0x192424C9},       /* DRAM address and Control Driving Strenght  */
  76        {0x000014C4, 0x0AAA24C9},       /* DRAM Data and DQS Driving Strenght  */
  77
  78        {0x000200e8, 0x3FFF0E01},       /* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence*/
  79        {0x00020184, 0x3FFFFFE0},       /* DO NOT Modify - Close fast path Window to - 2G */
  80
  81        {0x0001504, 0x3FFFFFE1},        /* CS0 Size */
  82        {0x000150C, 0x00000000},        /* CS1 Size */
  83        {0x0001514, 0x00000000},        /* CS2 Size */
  84        {0x000151C, 0x00000000},        /* CS3 Size */
  85
  86        {0x00001538, 0x00000009},       /*Read Data Sample Delays Register */
  87        {0x0000153C, 0x00000009},       /*Read Data Ready Delay Register */
  88
  89        {0x000015D0, 0x00000650},       /*MR0 */
  90        {0x000015D4, 0x00000044},       /*MR1 */
  91        {0x000015D8, 0x00000010},       /*MR2 */
  92        {0x000015DC, 0x00000000},       /*MR3 */
  93
  94        {0x000015E4, 0x00203c18},       /*ZQC Configuration Register */
  95        {0x000015EC, 0xF800A225},       /*DDR PHY */
  96
  97        {0x0, 0x0}
  98};
  99
 100MV_DRAM_MODES ds414_ddr_modes[MV_DDR3_MODES_NUMBER] = {
 101        {"ds414_1333-667",   0x3, 0x5, 0x0, A0, syno_ddr3_b0_667_1g_v1,  NULL},
 102};
 103
 104extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[];
 105
 106MV_BIN_SERDES_CFG ds414_serdes_cfg[] = {
 107        { MV_PEX_ROOT_COMPLEX, 0x02011111, 0x00000000,
 108          { PEX_BUS_MODE_X4, PEX_BUS_MODE_X1, PEX_BUS_DISABLED,
 109            PEX_BUS_DISABLED },
 110          0x0040, serdes_change_m_phy
 111        }
 112};
 113
 114MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
 115{
 116        return &ds414_ddr_modes[0];
 117}
 118
 119MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
 120{
 121        return &ds414_serdes_cfg[0];
 122}
 123
 124u8 board_sat_r_get(u8 dev_num, u8 reg)
 125{
 126        return (0x1 << 1 | 1);
 127}
 128
 129int board_early_init_f(void)
 130{
 131        int i;
 132
 133        /* Set GPP Out value */
 134        reg_write(GPP_DATA_OUT_REG(0), DS414_GPP_OUT_VAL_LOW);
 135        reg_write(GPP_DATA_OUT_REG(1), DS414_GPP_OUT_VAL_MID);
 136        reg_write(GPP_DATA_OUT_REG(2), DS414_GPP_OUT_VAL_HIGH);
 137
 138        /* set GPP polarity */
 139        reg_write(GPP_DATA_IN_POL_REG(0), DS414_GPP_OUT_POL_LOW);
 140        reg_write(GPP_DATA_IN_POL_REG(1), DS414_GPP_OUT_POL_MID);
 141        reg_write(GPP_DATA_IN_POL_REG(2), DS414_GPP_OUT_POL_HIGH);
 142
 143        /* Set GPP Out Enable */
 144        reg_write(GPP_DATA_OUT_EN_REG(0), DS414_GPP_OUT_ENA_LOW);
 145        reg_write(GPP_DATA_OUT_EN_REG(1), DS414_GPP_OUT_ENA_MID);
 146        reg_write(GPP_DATA_OUT_EN_REG(2), DS414_GPP_OUT_ENA_HIGH);
 147
 148        for (i = 0; i < ARRAY_SIZE(ds414_mpp_control); i++)
 149                reg_write(MPP_CONTROL_REG(i), ds414_mpp_control[i]);
 150
 151        return 0;
 152}
 153
 154int board_init(void)
 155{
 156        u32 pwr_mng_ctrl_reg;
 157
 158        /* Adress of boot parameters */
 159        gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 160
 161        /* Gate unused clocks
 162         *
 163         * Note: Disabling unused PCIe lanes will hang PCI bus scan.
 164         *       Once this is resolved, bits 10-12, 26 and 27 can be
 165         *       unset here as well.
 166         */
 167        pwr_mng_ctrl_reg = reg_read(POWER_MNG_CTRL_REG);
 168        pwr_mng_ctrl_reg &= ~(BIT(0));                          /* Audio */
 169        pwr_mng_ctrl_reg &= ~(BIT(1) | BIT(2));                 /* GE3, GE2 */
 170        pwr_mng_ctrl_reg &= ~(BIT(14) | BIT(15));               /* SATA0 link and core */
 171        pwr_mng_ctrl_reg &= ~(BIT(16));                         /* LCD */
 172        pwr_mng_ctrl_reg &= ~(BIT(17));                         /* SDIO */
 173        pwr_mng_ctrl_reg &= ~(BIT(19) | BIT(20));               /* USB1 and USB2 */
 174        pwr_mng_ctrl_reg &= ~(BIT(29) | BIT(30));               /* SATA1 link and core */
 175        reg_write(POWER_MNG_CTRL_REG, pwr_mng_ctrl_reg);
 176
 177        return 0;
 178}
 179
 180int checkboard(void)
 181{
 182        puts("Board: DS414\n");
 183
 184        return 0;
 185}
 186