LXR uboot/board/alphaproject/ap_sh4a_4a/ap_sh4a

   1/*
   2 * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
   3 * Copyright (C) 2012 Renesas Solutions Corp.
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8#include <common.h>
   9#include <asm/io.h>
  10#include <asm/processor.h>
  11#include <netdev.h>
  12#include <i2c.h>
  13
  14#define MODEMR                  (0xFFCC0020)
  15#define MODEMR_MASK             (0x6)
  16#define MODEMR_533MHZ   (0x2)
  17
  18int checkboard(void)
  19{
  20        u32 r = readl(MODEMR);
  21        if ((r & MODEMR_MASK) & MODEMR_533MHZ)
  22                puts("CPU Clock: 533MHz\n");
  23        else
  24                puts("CPU Clock: 400MHz\n");
  25
  26        puts("BOARD: Alpha Project. AP-SH4A-4A\n");
  27        return 0;
  28}
  29
  30#define MSTPSR1                 (0xFFC80044)
  31#define MSTPCR1                 (0xFFC80034)
  32#define MSTPSR1_GETHER  (1 << 14)
  33
  34/* IPSR3 */
  35#define ET0_ETXD0 (0x4 << 3)
  36#define ET0_GTX_CLK_A (0x4 << 6)
  37#define ET0_ETXD1_A (0x4 << 9)
  38#define ET0_ETXD2_A (0x4 << 12)
  39#define ET0_ETXD3_A (0x4 << 15)
  40#define ET0_ETXD4 (0x3 << 18)
  41#define ET0_ETXD5_A (0x5 << 21)
  42#define ET0_ETXD6_A (0x5 << 24)
  43#define ET0_ETXD7 (0x4 << 27)
  44#define IPSR3_ETH_ENABLE \
  45        (ET0_ETXD0 | ET0_GTX_CLK_A | ET0_ETXD1_A | ET0_ETXD2_A | \
  46        ET0_ETXD3_A | ET0_ETXD4 | ET0_ETXD5_A | ET0_ETXD6_A | ET0_ETXD7)
  47
  48/* IPSR4 */
  49#define ET0_ERXD7       (0x4)
  50#define ET0_RX_DV       (0x4 << 3)
  51#define ET0_RX_ER       (0x4 << 6)
  52#define ET0_CRS         (0x4 << 9)
  53#define ET0_COL         (0x4 << 12)
  54#define ET0_MDC         (0x4 << 15)
  55#define ET0_MDIO_A      (0x3 << 18)
  56#define ET0_LINK_A      (0x3 << 20)
  57#define ET0_PHY_INT_A (0x3 << 24)
  58
  59#define IPSR4_ETH_ENABLE \
  60        (ET0_ERXD7 | ET0_RX_DV | ET0_RX_ER | ET0_CRS | ET0_COL | \
  61        ET0_MDC | ET0_MDIO_A | ET0_LINK_A | ET0_PHY_INT_A)
  62
  63/* IPSR8 */
  64#define ET0_ERXD0       (0x4 << 20)
  65#define ET0_ERXD1       (0x4 << 23)
  66#define ET0_ERXD2_A (0x3 << 26)
  67#define ET0_ERXD3_A (0x3 << 28)
  68#define IPSR8_ETH_ENABLE \
  69        (ET0_ERXD0 | ET0_ERXD1 | ET0_ERXD2_A | ET0_ERXD3_A)
  70
  71/* IPSR10 */
  72#define RX4_D   (0x1 << 22)
  73#define TX4_D   (0x1 << 23)
  74#define IPSR10_SCIF_ENABLE (RX4_D | TX4_D)
  75
  76/* IPSR11 */
  77#define ET0_ERXD4       (0x4 <<  4)
  78#define ET0_ERXD5       (0x4 <<  7)
  79#define ET0_ERXD6       (0x3 << 10)
  80#define ET0_TX_EN       (0x2 << 19)
  81#define ET0_TX_ER       (0x2 << 21)
  82#define ET0_TX_CLK_A (0x4 << 23)
  83#define ET0_RX_CLK_A (0x3 << 26)
  84#define IPSR11_ETH_ENABLE \
  85        (ET0_ERXD4 | ET0_ERXD5 | ET0_ERXD6 | ET0_TX_EN | ET0_TX_ER | \
  86        ET0_TX_CLK_A | ET0_RX_CLK_A)
  87
  88#define GPSR1_INIT (0xFFFF7FFF)
  89#define GPSR2_INIT (0x4005FEFF)
  90#define GPSR3_INIT (0x2EFFFFFF)
  91#define GPSR4_INIT (0xC7000000)
  92
  93int board_init(void)
  94{
  95        u32 data;
  96
  97        /* Set IPSR register */
  98        data = readl(IPSR3);
  99        data |= IPSR3_ETH_ENABLE;
 100        writel(~data, PMMR);
 101        writel(data, IPSR3);
 102
 103        data = readl(IPSR4);
 104        data |= IPSR4_ETH_ENABLE;
 105        writel(~data, PMMR);
 106        writel(data, IPSR4);
 107
 108        data = readl(IPSR8);
 109        data |= IPSR8_ETH_ENABLE;
 110        writel(~data, PMMR);
 111        writel(data, IPSR8);
 112
 113        data = readl(IPSR10);
 114        data |= IPSR10_SCIF_ENABLE;
 115        writel(~data, PMMR);
 116        writel(data, IPSR10);
 117
 118        data = readl(IPSR11);
 119        data |= IPSR11_ETH_ENABLE;
 120        writel(~data, PMMR);
 121        writel(data, IPSR11);
 122
 123        /* GPIO select */
 124        data = GPSR1_INIT;
 125        writel(~data, PMMR);
 126        writel(data, GPSR1);
 127
 128        data = GPSR2_INIT;
 129        writel(~data, PMMR);
 130        writel(data, GPSR2);
 131
 132        data = GPSR3_INIT;
 133        writel(~data, PMMR);
 134        writel(data, GPSR3);
 135
 136        data = GPSR4_INIT;
 137        writel(~data, PMMR);
 138        writel(data, GPSR4);
 139
 140        data = 0x0;
 141        writel(~data, PMMR);
 142        writel(data, GPSR5);
 143
 144        /* mode select */
 145        data = MODESEL2_INIT;
 146        writel(~data, PMMR);
 147        writel(data, MODESEL2);
 148
 149#if defined(CONFIG_SH_ETHER)
 150        u32 r = readl(MSTPSR1);
 151        if (r & MSTPSR1_GETHER)
 152                writel((r & ~MSTPSR1_GETHER), MSTPCR1);
 153#endif
 154        return 0;
 155}
 156
 157int board_late_init(void)
 158{
 159        u8 mac[6];
 160
 161        /* Read Mac Address and set*/
 162        i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 163        i2c_set_bus_num(CONFIG_SYS_I2C_MODULE);
 164
 165        /* Read MAC address */
 166        i2c_read(0x50, 0x0, 0, mac, 6);
 167
 168        if (is_valid_ethaddr(mac))
 169                eth_setenv_enetaddr("ethaddr", mac);
 170
 171        return 0;
 172}
 173