LXR uboot/board/esd/vme8349/pci.c

   1/*
   2 * pci.c -- esd VME8349 PCI board support.
   3 * Copyright (c) 2006 Wind River Systems, Inc.
   4 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
   5 * Copyright (c) 2009 esd gmbh.
   6 *
   7 * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
   8 *
   9 * Based on MPC8349 PCI support but w/o PIB related code.
  10 *
  11 * SPDX-License-Identifier:     GPL-2.0+
  12 */
  13
  14#include <asm/mmu.h>
  15#include <asm/io.h>
  16#include <common.h>
  17#include <mpc83xx.h>
  18#include <pci.h>
  19#include <i2c.h>
  20#include <asm/fsl_i2c.h>
  21#include "vme8349pin.h"
  22
  23DECLARE_GLOBAL_DATA_PTR;
  24
  25static struct pci_region pci1_regions[] = {
  26        {
  27                bus_start: CONFIG_SYS_PCI1_MEM_BASE,
  28                phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
  29                size: CONFIG_SYS_PCI1_MEM_SIZE,
  30                flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
  31        },
  32        {
  33                bus_start: CONFIG_SYS_PCI1_IO_BASE,
  34                phys_start: CONFIG_SYS_PCI1_IO_PHYS,
  35                size: CONFIG_SYS_PCI1_IO_SIZE,
  36                flags: PCI_REGION_IO
  37        },
  38        {
  39                bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
  40                phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
  41                size: CONFIG_SYS_PCI1_MMIO_SIZE,
  42                flags: PCI_REGION_MEM
  43        },
  44};
  45
  46/*
  47 * pci_init_board()
  48 *
  49 * NOTICE: PCI2 is not supported. There is only one
  50 * physical PCI slot on the board.
  51 *
  52 */
  53void
  54pci_init_board(void)
  55{
  56        volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
  57        volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
  58        volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
  59        struct pci_region *reg[] = { pci1_regions };
  60        u8 reg8;
  61        int monarch = 0;
  62
  63        i2c_set_bus_num(1);
  64        /* Read the PCI_M66EN jumper setting */
  65        if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &reg8, 1) == 0) ||
  66            (i2c_read(0x38                     , 0, 0, &reg8, 1) == 0)) {
  67                if (reg8 & 0x40) {
  68                        clk->occr = 0xff000000; /* 66 MHz PCI */
  69                        printf("PCI:   66MHz\n");
  70                } else {
  71                        clk->occr = 0xffff0003; /* 33 MHz PCI */
  72                        printf("PCI:   33MHz\n");
  73                }
  74                if (((reg8 & 0x01) == 0) || ((reg8 & 0x02) == 0))
  75                        monarch = 1;
  76        } else {
  77                clk->occr = 0xffff0003; /* 33 MHz PCI */
  78                printf("PCI:   33MHz (I2C read failed)\n");
  79        }
  80        udelay(2000);
  81
  82        /*
  83         * Assert/deassert VME reset
  84         */
  85        clrsetbits_be32(&immr->gpio[1].dat,
  86                        GPIO2_TSI_POWERUP_RESET_N | GPIO2_TSI_PLL_RESET_N,
  87                        GPIO2_VME_RESET_N  | GPIO2_L_RESET_EN_N);
  88        setbits_be32(&immr->gpio[1].dir, GPIO2_TSI_PLL_RESET_N |
  89                     GPIO2_TSI_POWERUP_RESET_N |
  90                     GPIO2_VME_RESET_N |
  91                     GPIO2_L_RESET_EN_N);
  92        clrbits_be32(&immr->gpio[1].dir, GPIO2_V_SCON);
  93        udelay(200);
  94        setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_PLL_RESET_N);
  95        udelay(200);
  96        setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_POWERUP_RESET_N);
  97        udelay(600000);
  98        clrbits_be32(&immr->gpio[1].dat, GPIO2_L_RESET_EN_N);
  99
 100        /* Configure PCI Local Access Windows */
 101        pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
 102        pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
 103
 104        pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
 105        pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
 106
 107        udelay(2000);
 108
 109        if (monarch == 0) {
 110                mpc83xx_pci_init(1, reg);
 111        } else {
 112                /*
 113                 * Release PCI RST Output signal
 114                 */
 115                out_be32(&immr->pci_ctrl[0].gcr, 0);
 116                udelay(2000);
 117                out_be32(&immr->pci_ctrl[0].gcr, 1);
 118        }
 119}
 120