LXR uboot/board/freescale/ls1043ardb/cpld.c

   1/*
   2 * Copyright 2015 Freescale Semiconductor
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 *
   6 * Freescale LS1043ARDB board-specific CPLD controlling supports.
   7 */
   8
   9#include <common.h>
  10#include <command.h>
  11#include <asm/io.h>
  12#include "cpld.h"
  13
  14u8 cpld_read(unsigned int reg)
  15{
  16        void *p = (void *)CONFIG_SYS_CPLD_BASE;
  17
  18        return in_8(p + reg);
  19}
  20
  21void cpld_write(unsigned int reg, u8 value)
  22{
  23        void *p = (void *)CONFIG_SYS_CPLD_BASE;
  24
  25        out_8(p + reg, value);
  26}
  27
  28/* Set the boot bank to the alternate bank */
  29void cpld_set_altbank(void)
  30{
  31        u16 reg = CPLD_CFG_RCW_SRC_NOR;
  32        u8 reg4 = CPLD_READ(soft_mux_on);
  33        u8 reg5 = (u8)(reg >> 1);
  34        u8 reg6 = (u8)(reg & 1);
  35        u8 reg7 = CPLD_READ(vbank);
  36
  37        cpld_rev_bit(&reg5);
  38
  39        CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
  40
  41        CPLD_WRITE(cfg_rcw_src1, reg5);
  42        CPLD_WRITE(cfg_rcw_src2, reg6);
  43
  44        reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK;
  45        CPLD_WRITE(vbank, reg7);
  46
  47        CPLD_WRITE(system_rst, 1);
  48}
  49
  50/* Set the boot bank to the default bank */
  51void cpld_set_defbank(void)
  52{
  53        u16 reg = CPLD_CFG_RCW_SRC_NOR;
  54        u8 reg4 = CPLD_READ(soft_mux_on);
  55        u8 reg5 = (u8)(reg >> 1);
  56        u8 reg6 = (u8)(reg & 1);
  57
  58        cpld_rev_bit(&reg5);
  59
  60        CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
  61
  62        CPLD_WRITE(cfg_rcw_src1, reg5);
  63        CPLD_WRITE(cfg_rcw_src2, reg6);
  64
  65        CPLD_WRITE(vbank, 0);
  66
  67        CPLD_WRITE(system_rst, 1);
  68}
  69
  70void cpld_set_nand(void)
  71{
  72        u16 reg = CPLD_CFG_RCW_SRC_NAND;
  73        u8 reg5 = (u8)(reg >> 1);
  74        u8 reg6 = (u8)(reg & 1);
  75
  76        cpld_rev_bit(&reg5);
  77
  78        CPLD_WRITE(soft_mux_on, 1);
  79
  80        CPLD_WRITE(cfg_rcw_src1, reg5);
  81        CPLD_WRITE(cfg_rcw_src2, reg6);
  82
  83        CPLD_WRITE(system_rst, 1);
  84}
  85
  86void cpld_set_sd(void)
  87{
  88        u16 reg = CPLD_CFG_RCW_SRC_SD;
  89        u8 reg5 = (u8)(reg >> 1);
  90        u8 reg6 = (u8)(reg & 1);
  91
  92        cpld_rev_bit(&reg5);
  93
  94        CPLD_WRITE(soft_mux_on, 1);
  95
  96        CPLD_WRITE(cfg_rcw_src1, reg5);
  97        CPLD_WRITE(cfg_rcw_src2, reg6);
  98
  99        CPLD_WRITE(system_rst, 1);
 100}
 101#ifdef DEBUG
 102static void cpld_dump_regs(void)
 103{
 104        printf("cpld_ver        = %x\n", CPLD_READ(cpld_ver));
 105        printf("cpld_ver_sub    = %x\n", CPLD_READ(cpld_ver_sub));
 106        printf("pcba_ver        = %x\n", CPLD_READ(pcba_ver));
 107        printf("soft_mux_on     = %x\n", CPLD_READ(soft_mux_on));
 108        printf("cfg_rcw_src1    = %x\n", CPLD_READ(cfg_rcw_src1));
 109        printf("cfg_rcw_src2    = %x\n", CPLD_READ(cfg_rcw_src2));
 110        printf("vbank           = %x\n", CPLD_READ(vbank));
 111        printf("sysclk_sel      = %x\n", CPLD_READ(sysclk_sel));
 112        printf("uart_sel        = %x\n", CPLD_READ(uart_sel));
 113        printf("sd1refclk_sel   = %x\n", CPLD_READ(sd1refclk_sel));
 114        printf("tdmclk_mux_sel  = %x\n", CPLD_READ(tdmclk_mux_sel));
 115        printf("sdhc_spics_sel  = %x\n", CPLD_READ(sdhc_spics_sel));
 116        printf("status_led      = %x\n", CPLD_READ(status_led));
 117        putc('\n');
 118}
 119#endif
 120
 121void cpld_rev_bit(unsigned char *value)
 122{
 123        u8 rev_val, val;
 124        int i;
 125
 126        val = *value;
 127        rev_val = val & 1;
 128        for (i = 1; i <= 7; i++) {
 129                val >>= 1;
 130                rev_val <<= 1;
 131                rev_val |= val & 1;
 132        }
 133
 134        *value = rev_val;
 135}
 136
 137int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 138{
 139        int rc = 0;
 140
 141        if (argc <= 1)
 142                return cmd_usage(cmdtp);
 143
 144        if (strcmp(argv[1], "reset") == 0) {
 145                if (strcmp(argv[2], "altbank") == 0)
 146                        cpld_set_altbank();
 147                else if (strcmp(argv[2], "nand") == 0)
 148                        cpld_set_nand();
 149                else if (strcmp(argv[2], "sd") == 0)
 150                        cpld_set_sd();
 151                else
 152                        cpld_set_defbank();
 153#ifdef DEBUG
 154        } else if (strcmp(argv[1], "dump") == 0) {
 155                cpld_dump_regs();
 156#endif
 157        } else {
 158                rc = cmd_usage(cmdtp);
 159        }
 160
 161        return rc;
 162}
 163
 164U_BOOT_CMD(
 165        cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
 166        "Reset the board or alternate bank",
 167        "reset: reset to default bank\n"
 168        "cpld reset altbank: reset to alternate bank\n"
 169        "cpld reset nand: reset to boot from NAND flash\n"
 170        "cpld reset sd: reset to boot from SD card\n"
 171#ifdef DEBUG
 172        "cpld dump - display the CPLD registers\n"
 173#endif
 174);
 175