1/** 2 * Copyright 2013 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * This file provides support for the ngPIXIS, a board-specific FPGA used on 7 * some Freescale reference boards. 8 */ 9 10/* 11 * CPLD register set. Feel free to add board-specific #ifdefs where necessary. 12 */ 13struct cpld_data { 14 u8 cpld_ver; /* 0x00 - CPLD Major Revision Register */ 15 u8 cpld_ver_sub; /* 0x01 - CPLD Minor Revision Register */ 16 u8 hw_ver; /* 0x02 - Hardware Revision Register */ 17 u8 sw_ver; /* 0x03 - Software Revision register */ 18 u8 res0[12]; /* 0x04 - 0x0F - not used */ 19 u8 reset_ctl1; /* 0x10 - Reset control Register1 */ 20 u8 reset_ctl2; /* 0x11 - Reset control Register2 */ 21 u8 int_status; /* 0x12 - Interrupt status Register */ 22 u8 flash_ctl_status; /* 0x13 - Flash control and status register */ 23 u8 fan_ctl_status; /* 0x14 - Fan control and status register */ 24#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) 25 u8 int_mask; /* 0x15 - Interrupt mask Register */ 26#else 27 u8 led_ctl_status; /* 0x15 - LED control and status register */ 28#endif 29 u8 sfp_ctl_status; /* 0x16 - SFP control and status register */ 30 u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/ 31 u8 boot_override; /* 0x18 - Boot override register */ 32 u8 boot_config1; /* 0x19 - Boot config override register*/ 33 u8 boot_config2; /* 0x1A - Boot config override register*/ 34} cpld_data_t; 35 36 37/* Pointer to the CPLD register set */ 38 39u8 cpld_read(unsigned int reg); 40void cpld_write(unsigned int reg, u8 value); 41 42#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) 43#define CPLD_WRITE(reg, value)\ 44 cpld_write(offsetof(struct cpld_data, reg), value) 45#define MISC_CTL_SG_SEL 0x80 46#define MISC_CTL_AURORA_SEL 0x02 47#define MISC_MUX_QE_TDM 0xc0 48