1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16#if 0
17#define DEBUG
18#endif
19
20#include <common.h>
21#include <asm/processor.h>
22#include <asm/mmu.h>
23#include <asm/io.h>
24#include <asm/cache.h>
25#include <asm/ppc440.h>
26#include <watchdog.h>
27
28DECLARE_GLOBAL_DATA_PTR;
29
30
31
32
33
34
35
36
37
38
39
40#ifdef CONFIG_4xx_DCACHE
41#define MY_TLB_WORD2_I_ENABLE 0
42#else
43#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE
44#endif
45
46
47
48
49extern int denali_wait_for_dlllock(void);
50extern void denali_core_search_data_eye(void);
51extern void dcbz_area(u32 start_address, u32 num_bytes);
52
53static u32 is_ecc_enabled(void)
54{
55 u32 val;
56
57 mfsdram(DDR0_22, val);
58 val &= DDR0_22_CTRL_RAW_MASK;
59 if (val)
60 return 1;
61 else
62 return 0;
63}
64
65void board_add_ram_info(int use_default)
66{
67 PPC4xx_SYS_INFO board_cfg;
68 u32 val;
69
70 if (is_ecc_enabled())
71 puts(" (ECC");
72 else
73 puts(" (ECC not");
74
75 get_sys_info(&board_cfg);
76 printf(" enabled, %ld MHz", (board_cfg.freqPLB * 2) / 1000000);
77
78 mfsdram(DDR0_03, val);
79 val = DDR0_03_CASLAT_DECODE(val);
80 printf(", CL%d)", val);
81}
82
83#ifdef CONFIG_DDR_ECC
84static void wait_ddr_idle(void)
85{
86
87
88
89
90}
91
92static void program_ecc(u32 start_address,
93 u32 num_bytes,
94 u32 tlb_word2_i_value)
95{
96 u32 val;
97 u32 current_addr = start_address;
98 u32 size;
99 int bytes_remaining;
100
101 sync();
102 wait_ddr_idle();
103
104
105
106
107
108 bytes_remaining = num_bytes - CONFIG_SYS_MEM_TOP_HIDE;
109
110
111
112
113
114
115 while (bytes_remaining > 0) {
116 size = min((64 << 20), bytes_remaining);
117
118
119 dcbz_area(current_addr, size);
120
121
122 clean_dcache_range(current_addr, current_addr + size);
123
124 current_addr += 64 << 20;
125 bytes_remaining -= 64 << 20;
126 WATCHDOG_RESET();
127 }
128
129 sync();
130 wait_ddr_idle();
131
132
133 mfsdram(DDR0_00, val);
134 mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
135
136
137 mfsdram(DDR0_01, val);
138 mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF));
139
140 sync();
141 wait_ddr_idle();
142}
143#endif
144
145
146
147
148
149
150int dram_init(void)
151{
152
153 mtsdram(DDR0_02, 0x00000000);
154
155 mtsdram(DDR0_00, 0x0000190A);
156 mtsdram(DDR0_01, 0x01000000);
157 mtsdram(DDR0_03, 0x02040803);
158
159 mtsdram(DDR0_04, 0x0B030300);
160 mtsdram(DDR0_05, 0x02020308);
161 mtsdram(DDR0_06, 0x0003C812);
162 mtsdram(DDR0_07, 0x00090100);
163 mtsdram(DDR0_08, 0x03c80001);
164 mtsdram(DDR0_09, 0x00011D5F);
165 mtsdram(DDR0_10, 0x00000100);
166 mtsdram(DDR0_11, 0x000CC800);
167 mtsdram(DDR0_12, 0x00000003);
168 mtsdram(DDR0_14, 0x00000000);
169 mtsdram(DDR0_17, 0x1e000000);
170 mtsdram(DDR0_18, 0x1e1e1e1e);
171 mtsdram(DDR0_19, 0x1e1e1e1e);
172 mtsdram(DDR0_20, 0x0B0B0B0B);
173 mtsdram(DDR0_21, 0x0B0B0B0B);
174#ifdef CONFIG_DDR_ECC
175 mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE);
176#else
177 mtsdram(DDR0_22, 0x00267F0B);
178#endif
179
180 mtsdram(DDR0_23, 0x01000000);
181 mtsdram(DDR0_24, 0x01010001);
182
183 mtsdram(DDR0_26, 0x2D93028A);
184 mtsdram(DDR0_27, 0x0784682B);
185
186 mtsdram(DDR0_28, 0x00000080);
187 mtsdram(DDR0_31, 0x00000000);
188 mtsdram(DDR0_42, 0x01000008);
189
190 mtsdram(DDR0_43, 0x050A0200);
191 mtsdram(DDR0_44, 0x00000005);
192 mtsdram(DDR0_02, 0x00000001);
193
194 denali_wait_for_dlllock();
195
196#if defined(CONFIG_DDR_DATA_EYE)
197
198
199
200 program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20,
201 TLB_WORD2_I_ENABLE);
202 denali_core_search_data_eye();
203 remove_tlb(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20);
204#endif
205
206
207
208
209 program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20,
210 MY_TLB_WORD2_I_ENABLE);
211
212#if defined(CONFIG_DDR_ECC)
213#if defined(CONFIG_4xx_DCACHE)
214
215
216
217 program_ecc(0, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
218#else
219
220
221
222
223 program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
224
225
226
227
228 program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
229
230
231
232
233
234
235 remove_tlb(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20);
236#endif
237#endif
238
239
240
241
242
243
244 set_mcsr(get_mcsr());
245
246 gd->ram_size = CONFIG_SYS_MBYTES_SDRAM << 20;
247
248 return 0;
249}
250