LXR uboot/board/samsung/smdkc100/onenand.c

   1/*
   2 * Copyright (C) 2008-2009 Samsung Electronics
   3 * Kyungmin Park <kyungmin.park@samsung.com>
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8#include <common.h>
   9#include <linux/compat.h>
  10#include <linux/mtd/mtd.h>
  11#include <linux/mtd/onenand.h>
  12#include <linux/mtd/samsung_onenand.h>
  13
  14#include <onenand_uboot.h>
  15
  16#include <asm/io.h>
  17#include <asm/arch/clock.h>
  18
  19int onenand_board_init(struct mtd_info *mtd)
  20{
  21        struct onenand_chip *this = mtd->priv;
  22        struct s5pc100_clock *clk =
  23                        (struct s5pc100_clock *)samsung_get_base_clock();
  24        struct samsung_onenand *onenand;
  25        int value;
  26
  27        this->base = (void *)S5PC100_ONENAND_BASE;
  28        onenand = (struct samsung_onenand *)this->base;
  29
  30        /* D0 Domain memory clock gating */
  31        value = readl(&clk->gate_d01);
  32        value &= ~(1 << 2);             /* CLK_ONENANDC */
  33        value |= (1 << 2);
  34        writel(value, &clk->gate_d01);
  35
  36        value = readl(&clk->src0);
  37        value &= ~(1 << 24);            /* MUX_1nand: 0 from HCLKD0 */
  38        value &= ~(1 << 20);            /* MUX_HREF: 0 from FIN_27M */
  39        writel(value, &clk->src0);
  40
  41        value = readl(&clk->div1);
  42        value &= ~(3 << 16);            /* PCLKD1_RATIO */
  43        value |= (1 << 16);
  44        writel(value, &clk->div1);
  45
  46        writel(ONENAND_MEM_RESET_COLD, &onenand->mem_reset);
  47
  48        while (!(readl(&onenand->int_err_stat) & RST_CMP))
  49                continue;
  50
  51        writel(RST_CMP, &onenand->int_err_ack);
  52
  53        /*
  54         * Access_Clock [2:0]
  55         * 166 MHz, 134 Mhz : 3
  56         * 100 Mhz, 60 Mhz  : 2
  57         */
  58        writel(0x3, &onenand->acc_clock);
  59
  60        writel(INT_ERR_ALL, &onenand->int_err_mask);
  61        writel(1 << 0, &onenand->int_pin_en);   /* Enable */
  62
  63        value = readl(&onenand->int_err_mask);
  64        value &= ~RDY_ACT;
  65        writel(value, &onenand->int_err_mask);
  66
  67        s3c_onenand_init(mtd);
  68
  69        return 0;
  70}
  71