LXR uboot/board/xes/common/fsl_8xxx

   1/*
   2 * Copyright 2008 Extreme Engineering Solutions, Inc.
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#include <common.h>
   8#include <asm/io.h>
   9
  10/*
  11 * Return SYSCLK input frequency - 50 MHz or 66 MHz depending on POR config
  12 */
  13unsigned long get_board_sys_clk(ulong dummy)
  14{
  15#if defined(CONFIG_MPC85xx)
  16        volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  17#elif defined(CONFIG_MPC86xx)
  18        immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  19        volatile ccsr_gur_t *gur = &immap->im_gur;
  20#endif
  21
  22        if (in_be32(&gur->gpporcr) & 0x10000)
  23                return 66666666;
  24        else
  25#ifdef CONFIG_ARCH_P2020
  26                return 100000000;
  27#else
  28                return 50000000;
  29#endif
  30}
  31
  32#ifdef CONFIG_MPC85xx
  33/*
  34 * Return DDR input clock - synchronous with SYSCLK or 66 MHz
  35 * Note: 86xx doesn't support asynchronous DDR clk
  36 */
  37unsigned long get_board_ddr_clk(ulong dummy)
  38{
  39        volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  40        u32 ddr_ratio = (in_be32(&gur->porpllsr) & 0x00003e00) >> 9;
  41
  42        if (ddr_ratio == 0x7)
  43                return get_board_sys_clk(dummy);
  44
  45#ifdef CONFIG_ARCH_P2020
  46        if (in_be32(&gur->gpporcr) & 0x20000)
  47                return 66666666;
  48        else
  49                return 100000000;
  50#else
  51        return 66666666;
  52#endif
  53}
  54#endif
  55