uboot/doc/README.srio-pcie-boot-corenet
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   2SRIO and PCIE Boot on Corenet Platforms
   3---------------------------------------
   4
   5For some PowerPC processors with SRIO or PCIE interface, boot location can be
   6configured to SRIO or PCIE by RCW. The processor booting from SRIO or PCIE can
   7do without flash for u-boot image, ucode and ENV. All the images can be fetched
   8from another processor's memory space by SRIO or PCIE link connected between
   9them.
  10
  11This document describes the processes based on an example implemented on P4080DS
  12platforms and a RCW example with boot from SRIO or PCIE configuration.
  13
  14Environment of the SRIO or PCIE boot:
  15        a) Master and slave can be SOCs in one board or SOCs in separate boards.
  16        b) They are connected with SRIO or PCIE links, whether 1x, 2x or 4x, and
  17           directly or through switch system.
  18        c) Only Master has NorFlash for booting, and all the Master's and Slave's
  19           U-Boot images, UCodes will be stored in this flash.
  20        d) Slave has its own EEPROM for RCW and PBI.
  21        e) Slave's RCW should configure the SerDes for SRIO or PCIE boot port, set
  22           the boot location to SRIO or PCIE, and holdoff all the cores.
  23
  24        -----------       -----------             -----------
  25        |         |       |         |             |         |
  26        |         |       |         |             |         |
  27        | NorFlash|<----->| Master  |SRIO or PCIE |  Slave  |<---->[EEPROM]
  28        |         |       |         |<===========>|         |
  29        |         |       |         |             |         |
  30        -----------       -----------             -----------
  31
  32The example based on P4080DS platform:
  33        Two P4080DS platforms can be used to implement the boot from SRIO or PCIE.
  34        Their SRIO or PCIE ports 1 will be connected directly and will be used for
  35        the boot from SRIO or PCIE.
  36
  37        1. Slave's RCW example for boot from SRIO port 1 and all cores in holdoff.
  38                00000000: aa55 aa55 010e 0100 0c58 0000 0000 0000
  39                00000010: 1818 1818 0000 8888 7440 4000 0000 2000
  40                00000020: f440 0000 0100 0000 0000 0000 0000 0000
  41                00000030: 0000 0000 0083 0000 0000 0000 0000 0000
  42                00000040: 0000 0000 0000 0000 0813 8040 063c 778f
  43
  44        2. Slave's RCW example for boot from PCIE port 1 and all cores in holdoff.
  45                00000000: aa55 aa55 010e 0100 0c58 0000 0000 0000
  46                00000010: 1818 1818 0000 8888 1440 4000 0000 2000
  47                00000020: f040 0000 0100 0000 0020 0000 0000 0000
  48                00000030: 0000 0000 0083 0000 0000 0000 0000 0000
  49                00000040: 0000 0000 0000 0000 0813 8040 547e ffc9
  50
  51        3. Sequence in Step by Step.
  52                a) Update RCW for slave with boot from SRIO or PCIE port 1 configuration.
  53                b) Program slave's U-Boot image, UCode, and ENV parameters into master's
  54                   NorFlash.
  55                c) Set environment variable "bootmaster" to "SRIO1" or "PCIE1" and save
  56                   environment for master.
  57                                        setenv bootmaster SRIO1
  58                                or
  59                                        setenv bootmaster PCIE1
  60                                        saveenv
  61                d) Restart up master and it will boot up normally from its NorFlash.
  62                   Then, it will finish necessary configurations for slave's boot from
  63                   SRIO or PCIE port 1.
  64                e) Master will set inbound SRIO or PCIE windows covered slave's U-Boot
  65                   image stored in master's NorFlash.
  66                f) Master will set an inbound SRIO or PCIE window covered slave's UCode
  67                   and ENV stored in master's NorFlash.
  68                g) Master will set outbound SRIO or PCIE  windows in order to configure
  69                   slave's registers for the core's releasing.
  70                h) Since all cores of slave in holdoff, slave should be powered on before
  71                   all the above master's steps, and wait to be released by master. In the
  72                   startup phase of the slave from SRIO or PCIE, it will finish some
  73                   necessary configurations.
  74                i) Slave will set a specific TLB entry for the boot process.
  75                j) Slave will set a LAW entry with the TargetID SRIO or PCIE port 1 for
  76                   the boot.
  77                k) Slave will set a specific TLB entry in order to fetch UCode and ENV
  78                   from master.
  79                l) Slave will set a LAW entry with the TargetID SRIO or PCIE port 1 for
  80                   UCode and ENV.
  81
  82How to use this feature:
  83        To use this feature, you need to focus those points.
  84
  85        1. Slave's RCW with SRIO or PCIE boot configurations, and all cores in holdoff
  86           configurations.
  87           Please refer to the examples given above.
  88
  89        2. U-Boot image's compilation.
  90           For master, U-Boot image should be generated normally.
  91
  92           For example, master U-Boot image used on P4080DS should be compiled with
  93
  94                                make P4080DS_config.
  95
  96           For slave, U-Boot image should be generated specifically by
  97
  98                                make xxxx_SRIO_PCIE_BOOT_config.
  99
 100           For example, slave U-Boot image used on P4080DS should be compiled with
 101
 102                                make P4080DS_SRIO_PCIE_BOOT_config.
 103
 104        3. Necessary modifications based on a specific environment.
 105           For a specific environment, the addresses of the slave's U-Boot image,
 106           UCode, ENV stored in master's NorFlash, and any other configurations
 107           can be modified in the file:
 108                                include/configs/corenet_ds.h.
 109
 110        4. Set and save the environment variable "bootmaster" with "SRIO1", "SRIO2"
 111           or "PCIE1", "PCIE2", "PCIE3" for master, and then restart it in order to
 112           perform the role as a master for boot from SRIO or PCIE.
 113
 114NOTE: When the Slave's ENV parameters are stored in Master's NorFlash,
 115      it can fetch them through PCIE or SRIO interface. But the ENV
 116      parameters can not be modified by "saveenv" or other commands under
 117      the Slave's u-boot environment, because the Slave can not erase,
 118      write Master's NorFlash by PCIE or SRIO link.
 119