LXR uboot/drivers/phy/marvell/comphy.h

   1/*
   2 * Copyright (C) 2015-2016 Marvell International Ltd.
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#ifndef _COMPHY_H_
   8#define _COMPHY_H_
   9
  10#include <dt-bindings/comphy/comphy_data.h>
  11#include <fdtdec.h>
  12
  13#if defined(DEBUG)
  14#define debug_enter()   printf("----> Enter %s\n", __func__);
  15#define debug_exit()    printf("<---- Exit  %s\n", __func__);
  16#else
  17#define debug_enter()
  18#define debug_exit()
  19#endif
  20
  21/* COMPHY registers */
  22#define COMMON_PHY_CFG1_REG                     0x0
  23#define COMMON_PHY_CFG1_PWR_UP_OFFSET           1
  24#define COMMON_PHY_CFG1_PWR_UP_MASK             \
  25        (0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET)
  26#define COMMON_PHY_CFG1_PIPE_SELECT_OFFSET      2
  27#define COMMON_PHY_CFG1_PIPE_SELECT_MASK        \
  28        (0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET)
  29#define COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET     13
  30#define COMMON_PHY_CFG1_PWR_ON_RESET_MASK       \
  31        (0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET)
  32#define COMMON_PHY_CFG1_CORE_RSTN_OFFSET        14
  33#define COMMON_PHY_CFG1_CORE_RSTN_MASK          \
  34        (0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET)
  35#define COMMON_PHY_PHY_MODE_OFFSET              15
  36#define COMMON_PHY_PHY_MODE_MASK                \
  37        (0x1 << COMMON_PHY_PHY_MODE_OFFSET)
  38
  39#define COMMON_PHY_CFG6_REG                     0x14
  40#define COMMON_PHY_CFG6_IF_40_SEL_OFFSET        18
  41#define COMMON_PHY_CFG6_IF_40_SEL_MASK          \
  42        (0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET)
  43
  44#define COMMON_SELECTOR_PHY_OFFSET              0x140
  45#define COMMON_SELECTOR_PIPE_OFFSET             0x144
  46
  47#define COMMON_PHY_SD_CTRL1                     0x148
  48#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET      0
  49#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK        0xFFFF
  50#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET   24
  51#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK     \
  52        (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET)
  53#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET   25
  54#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK     \
  55        (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET)
  56#define COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET       26
  57#define COMMON_PHY_SD_CTRL1_RXAUI1_MASK         \
  58        (0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET)
  59#define COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET       27
  60#define COMMON_PHY_SD_CTRL1_RXAUI0_MASK         \
  61        (0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET)
  62
  63/* ToDo: Get this address via DT */
  64#define MVEBU_CP0_REGS_BASE                     0xF2000000UL
  65
  66#define DFX_DEV_GEN_CTRL12                      (MVEBU_CP0_REGS_BASE + 0x400280)
  67#define DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET         7
  68#define DFX_DEV_GEN_PCIE_CLK_SRC_MASK           \
  69        (0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET)
  70
  71#define MAX_LANE_OPTIONS                        10
  72#define MAX_UTMI_PHY_COUNT                      3
  73
  74struct comphy_mux_options {
  75        u32 type;
  76        u32 mux_value;
  77};
  78
  79struct comphy_mux_data {
  80        u32 max_lane_values;
  81        struct comphy_mux_options mux_values[MAX_LANE_OPTIONS];
  82};
  83
  84struct comphy_map {
  85        u32 type;
  86        u32 speed;
  87        u32 invert;
  88        bool clk_src;
  89};
  90
  91struct chip_serdes_phy_config {
  92        struct comphy_mux_data *mux_data;
  93        int (*ptr_comphy_chip_init)(struct chip_serdes_phy_config *,
  94                                    struct comphy_map *);
  95        void __iomem *comphy_base_addr;
  96        void __iomem *hpipe3_base_addr;
  97        u32 comphy_lanes_count;
  98        u32 comphy_mux_bitcount;
  99        u32 comphy_index;
 100};
 101
 102/* Register helper functions */
 103void reg_set(void __iomem *addr, u32 data, u32 mask);
 104void reg_set_silent(void __iomem *addr, u32 data, u32 mask);
 105void reg_set16(void __iomem *addr, u16 data, u16 mask);
 106void reg_set_silent16(void __iomem *addr, u16 data, u16 mask);
 107
 108/* SoC specific init functions */
 109#ifdef CONFIG_ARMADA_3700
 110int comphy_a3700_init(struct chip_serdes_phy_config *ptr_chip_cfg,
 111                      struct comphy_map *serdes_map);
 112#else
 113static inline int comphy_a3700_init(struct chip_serdes_phy_config *ptr_chip_cfg,
 114                                    struct comphy_map *serdes_map)
 115{
 116        /*
 117         * This function should never be called in this configuration, so
 118         * lets return an error here.
 119         */
 120        return -1;
 121}
 122#endif
 123
 124#ifdef CONFIG_ARMADA_8K
 125int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
 126                      struct comphy_map *serdes_map);
 127#else
 128static inline int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
 129                      struct comphy_map *serdes_map)
 130{
 131        /*
 132         * This function should never be called in this configuration, so
 133         * lets return an error here.
 134         */
 135        return -1;
 136}
 137#endif
 138
 139void comphy_dedicated_phys_init(void);
 140
 141/* MUX function */
 142void comphy_mux_init(struct chip_serdes_phy_config *ptr_chip_cfg,
 143                     struct comphy_map *comphy_map_data,
 144                     void __iomem *selector_base);
 145
 146void comphy_pcie_config_set(u32 comphy_max_count,
 147                            struct comphy_map *serdes_map);
 148void comphy_pcie_config_detect(u32 comphy_max_count,
 149                               struct comphy_map *serdes_map);
 150void comphy_pcie_unit_general_config(u32 pex_index);
 151
 152#endif /* _COMPHY_H_ */
 153
 154