1/* 2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 3 * Hayden Fraser (Hayden.Fraser@freescale.com) 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8#ifndef _M5253EVBE_H 9#define _M5253EVBE_H 10 11#define CONFIG_M5253EVBE /* define board type */ 12 13#define CONFIG_MCFTMR 14 15#define CONFIG_MCFUART 16#define CONFIG_SYS_UART_PORT (0) 17 18#undef CONFIG_WATCHDOG /* disable watchdog */ 19 20 21/* Configuration for environment 22 * Environment is embedded in u-boot in the second sector of the flash 23 */ 24#ifndef CONFIG_MONITOR_IS_IN_RAM 25#define CONFIG_ENV_OFFSET 0x4000 26#define CONFIG_ENV_SECT_SIZE 0x2000 27#define CONFIG_ENV_IS_IN_FLASH 1 28#else 29#define CONFIG_ENV_ADDR 0xffe04000 30#define CONFIG_ENV_SECT_SIZE 0x2000 31#define CONFIG_ENV_IS_IN_FLASH 1 32#endif 33 34#define LDS_BOARD_TEXT \ 35 . = DEFINED(env_offset) ? env_offset : .; \ 36 common/env_embedded.o (.text) 37 38/* 39 * BOOTP options 40 */ 41#undef CONFIG_BOOTP_BOOTFILESIZE 42#undef CONFIG_BOOTP_BOOTPATH 43#undef CONFIG_BOOTP_GATEWAY 44#undef CONFIG_BOOTP_HOSTNAME 45 46/* 47 * Command line configuration. 48 */ 49#define CONFIG_CMD_IDE 50 51/* ATA */ 52#define CONFIG_IDE_RESET 1 53#define CONFIG_IDE_PREINIT 1 54#define CONFIG_ATAPI 55#undef CONFIG_LBA48 56 57#define CONFIG_SYS_IDE_MAXBUS 1 58#define CONFIG_SYS_IDE_MAXDEVICE 2 59 60#define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800) 61#define CONFIG_SYS_ATA_IDE0_OFFSET 0 62 63#define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ 64#define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ 65#define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ 66#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ 67 68#define CONFIG_SYS_LONGHELP /* undef to save memory */ 69 70#if defined(CONFIG_CMD_KGDB) 71#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 72#else 73#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 74#endif 75#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 76#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 77#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 78 79#define CONFIG_SYS_LOAD_ADDR 0x00100000 80 81#define CONFIG_SYS_MEMTEST_START 0x400 82#define CONFIG_SYS_MEMTEST_END 0x380000 83 84#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ 85#define CONFIG_SYS_FAST_CLK 86#ifdef CONFIG_SYS_FAST_CLK 87# define CONFIG_SYS_PLLCR 0x1243E054 88# define CONFIG_SYS_CLK 140000000 89#else 90# define CONFIG_SYS_PLLCR 0x135a4140 91# define CONFIG_SYS_CLK 70000000 92#endif 93 94/* 95 * Low Level Configuration Settings 96 * (address mappings, register initial values, etc.) 97 * You should know what you are doing if you make changes here. 98 */ 99 100#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 101#define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */ 102 103/* 104 * Definitions for initial stack pointer and data area (in DPRAM) 105 */ 106#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 107#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 108#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 109#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 110 111/* 112 * Start addresses for the final memory configuration 113 * (Set up by the startup code) 114 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 115 */ 116#define CONFIG_SYS_SDRAM_BASE 0x00000000 117#define CONFIG_SYS_SDRAM_SIZE 8 /* SDRAM size in MB */ 118 119#ifdef CONFIG_MONITOR_IS_IN_RAM 120#define CONFIG_SYS_MONITOR_BASE 0x20000 121#else 122#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 123#endif 124 125#define CONFIG_SYS_MONITOR_LEN 0x40000 126#define CONFIG_SYS_MALLOC_LEN (256 << 10) 127#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) 128 129/* 130 * For booting Linux, the board info and command line data 131 * have to be in the first 8 MB of memory, since this is 132 * the maximum mapped by the Linux kernel during initialization ?? 133 */ 134#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 135#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 136 137/* FLASH organization */ 138#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 139#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 140#define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ 141#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 142 143#define CONFIG_SYS_FLASH_CFI 1 144#define CONFIG_FLASH_CFI_DRIVER 1 145#define CONFIG_SYS_FLASH_SIZE 0x200000 146#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 147 148/* Cache Configuration */ 149#define CONFIG_SYS_CACHELINE_SIZE 16 150 151#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 152 CONFIG_SYS_INIT_RAM_SIZE - 8) 153#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 154 CONFIG_SYS_INIT_RAM_SIZE - 4) 155#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) 156#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ 157 CF_ADDRMASK(2) | \ 158 CF_ACR_EN | CF_ACR_SM_ALL) 159#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ 160 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 161 CF_ACR_EN | CF_ACR_SM_ALL) 162#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ 163 CF_CACR_DBWE) 164 165/* Port configuration */ 166#define CONFIG_SYS_FECI2C 0xF0 167 168#define CONFIG_SYS_CS0_BASE 0xFFE00000 169#define CONFIG_SYS_CS0_MASK 0x001F0021 170#define CONFIG_SYS_CS0_CTRL 0x00001D80 171 172/*----------------------------------------------------------------------- 173 * Port configuration 174 */ 175#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ 176#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ 177#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ 178#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ 179#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ 180#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ 181#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ 182 183#endif /* _M5253EVB_H */ 184