1
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5
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
10
11
12
13#define CONFIG_E300 1
14#define CONFIG_QE 1
15#define CONFIG_MPC832x 1
16#define CONFIG_MPC832XEMDS 1
17
18#define CONFIG_SYS_TEXT_BASE 0xFE000000
19
20
21
22
23#ifdef CONFIG_PCISLAVE
24#define CONFIG_83XX_PCICLK 66000000
25#else
26#define CONFIG_83XX_CLKIN 66000000
27#endif
28
29#ifndef CONFIG_SYS_CLK_FREQ
30#define CONFIG_SYS_CLK_FREQ 66000000
31#endif
32
33
34
35
36#define CONFIG_SYS_HRCW_LOW (\
37 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
38 HRCWL_DDR_TO_SCB_CLK_2X1 |\
39 HRCWL_VCO_1X2 |\
40 HRCWL_CSB_TO_CLKIN_2X1 |\
41 HRCWL_CORE_TO_CSB_2X1 |\
42 HRCWL_CE_PLL_VCO_DIV_2 |\
43 HRCWL_CE_PLL_DIV_1X1 |\
44 HRCWL_CE_TO_PLL_1X3)
45
46#ifdef CONFIG_PCISLAVE
47#define CONFIG_SYS_HRCW_HIGH (\
48 HRCWH_PCI_AGENT |\
49 HRCWH_PCI1_ARBITER_DISABLE |\
50 HRCWH_CORE_ENABLE |\
51 HRCWH_FROM_0XFFF00100 |\
52 HRCWH_BOOTSEQ_DISABLE |\
53 HRCWH_SW_WATCHDOG_DISABLE |\
54 HRCWH_ROM_LOC_LOCAL_16BIT |\
55 HRCWH_BIG_ENDIAN |\
56 HRCWH_LALE_NORMAL)
57#else
58#define CONFIG_SYS_HRCW_HIGH (\
59 HRCWH_PCI_HOST |\
60 HRCWH_PCI1_ARBITER_ENABLE |\
61 HRCWH_CORE_ENABLE |\
62 HRCWH_FROM_0X00000100 |\
63 HRCWH_BOOTSEQ_DISABLE |\
64 HRCWH_SW_WATCHDOG_DISABLE |\
65 HRCWH_ROM_LOC_LOCAL_16BIT |\
66 HRCWH_BIG_ENDIAN |\
67 HRCWH_LALE_NORMAL)
68#endif
69
70
71
72
73#define CONFIG_SYS_SICRL 0x00000000
74
75#define CONFIG_BOARD_EARLY_INIT_R
76
77
78
79
80#define CONFIG_SYS_IMMR 0xE0000000
81
82
83
84
85#define CONFIG_SYS_DDR_BASE 0x00000000
86#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
87#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
88#define CONFIG_SYS_DDRCDR 0x73000002
89
90#undef CONFIG_SPD_EEPROM
91#if defined(CONFIG_SPD_EEPROM)
92
93
94#define SPD_EEPROM_ADDRESS 0x51
95#else
96
97
98#define CONFIG_SYS_DDR_SIZE 128
99#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
100 | CSCONFIG_AP \
101 | CSCONFIG_ODT_WR_CFG \
102 | CSCONFIG_ROW_BIT_13 \
103 | CSCONFIG_COL_BIT_10)
104
105#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
106 | (0 << TIMING_CFG0_WRT_SHIFT) \
107 | (0 << TIMING_CFG0_RRT_SHIFT) \
108 | (0 << TIMING_CFG0_WWT_SHIFT) \
109 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
110 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
111 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
112 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
113
114#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
115 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
116 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
117 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
118 | (13 << TIMING_CFG1_REFREC_SHIFT) \
119 | (3 << TIMING_CFG1_WRREC_SHIFT) \
120 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
121 | (2 << TIMING_CFG1_WRTORD_SHIFT))
122
123#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
124 | (31 << TIMING_CFG2_CPO_SHIFT) \
125 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
126 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
127 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
128 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
129 | (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
130
131#define CONFIG_SYS_DDR_TIMING_3 0x00000000
132#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
133
134#define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
135 | (0x0232 << SDRAM_MODE_SD_SHIFT))
136
137#define CONFIG_SYS_DDR_MODE2 0x8000c000
138#define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
139 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
140
141#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
142#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
143 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
144 | SDRAM_CFG_32_BE)
145
146#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
147#endif
148
149
150
151
152#undef CONFIG_SYS_DRAM_TEST
153#define CONFIG_SYS_MEMTEST_START 0x00000000
154#define CONFIG_SYS_MEMTEST_END 0x00100000
155
156
157
158
159#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
160
161#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
162#define CONFIG_SYS_RAMBOOT
163#else
164#undef CONFIG_SYS_RAMBOOT
165#endif
166
167
168#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
169#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
170
171
172
173
174#define CONFIG_SYS_INIT_RAM_LOCK 1
175#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000
176#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
177#define CONFIG_SYS_GBL_DATA_OFFSET \
178 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
179
180
181
182
183#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
184#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
185#define CONFIG_SYS_LBC_LBCR 0x00000000
186
187
188
189
190#define CONFIG_SYS_FLASH_CFI
191#define CONFIG_FLASH_CFI_DRIVER
192#define CONFIG_SYS_FLASH_BASE 0xFE000000
193#define CONFIG_SYS_FLASH_SIZE 16
194#define CONFIG_SYS_FLASH_PROTECTION 1
195
196
197#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
198#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
199
200#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
201 | BR_PS_16 \
202 | BR_MS_GPCM \
203 | BR_V)
204#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
205 | OR_GPCM_XAM \
206 | OR_GPCM_CSNT \
207 | OR_GPCM_ACS_DIV2 \
208 | OR_GPCM_XACS \
209 | OR_GPCM_SCY_15 \
210 | OR_GPCM_TRLX_SET \
211 | OR_GPCM_EHTR_SET \
212 | OR_GPCM_EAD)
213
214
215#define CONFIG_SYS_MAX_FLASH_BANKS 1
216#define CONFIG_SYS_MAX_FLASH_SECT 128
217
218#undef CONFIG_SYS_FLASH_CHECKSUM
219
220
221
222
223#define CONFIG_SYS_BCSR 0xF8000000
224
225#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
226#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
227
228#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
229 | BR_PS_8 \
230 | BR_MS_GPCM \
231 | BR_V)
232#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
233 | OR_GPCM_XAM \
234 | OR_GPCM_CSNT \
235 | OR_GPCM_XACS \
236 | OR_GPCM_SCY_15 \
237 | OR_GPCM_TRLX_SET \
238 | OR_GPCM_EHTR_SET \
239 | OR_GPCM_EAD)
240
241
242
243
244
245
246#define CONFIG_SYS_PIB_BASE 0xF8008000
247#define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024)
248#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PIB_BASE
249#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
250
251
252
253
254#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_PIB_BASE \
255 | BR_PS_8 \
256 | BR_MS_GPCM \
257 | BR_V)
258
259#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
260 | OR_GPCM_XAM \
261 | OR_GPCM_CSNT \
262 | OR_GPCM_XACS \
263 | OR_GPCM_SCY_15 \
264 | OR_GPCM_TRLX_SET \
265 | OR_GPCM_EHTR_SET \
266 | OR_GPCM_EAD)
267
268
269
270
271
272#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIB_BASE + \
273 CONFIG_SYS_PIB_WINDOW_SIZE) \
274 | BR_PS_8 \
275 | BR_MS_GPCM \
276 | BR_V)
277
278#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
279 | OR_GPCM_XAM \
280 | OR_GPCM_CSNT \
281 | OR_GPCM_XACS \
282 | OR_GPCM_SCY_15 \
283 | OR_GPCM_TRLX_SET \
284 | OR_GPCM_EHTR_SET \
285 | OR_GPCM_EAD)
286
287
288
289
290
291#define CONFIG_CONS_INDEX 1
292#define CONFIG_SYS_NS16550_SERIAL
293#define CONFIG_SYS_NS16550_REG_SIZE 1
294#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
295
296#define CONFIG_SYS_BAUDRATE_TABLE \
297 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
298
299#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
300#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
301
302#define CONFIG_CMDLINE_EDITING 1
303#define CONFIG_AUTO_COMPLETE
304
305
306#define CONFIG_SYS_I2C
307#define CONFIG_SYS_I2C_FSL
308#define CONFIG_SYS_FSL_I2C_SPEED 400000
309#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
310#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
311#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
312
313
314
315
316#define CONFIG_RTC_DS1374
317#define CONFIG_SYS_I2C_RTC_ADDR 0x68
318
319
320
321
322
323#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
324#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
325#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
326#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
327#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
328#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
329#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
330#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
331#define CONFIG_SYS_PCI1_IO_SIZE 0x100000
332
333#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
334#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
335#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
336
337#ifdef CONFIG_PCI
338#define CONFIG_PCI_INDIRECT_BRIDGE
339
340#define CONFIG_83XX_PCI_STREAMING
341
342#undef CONFIG_EEPRO100
343#undef CONFIG_PCI_SCAN_SHOW
344#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957
345
346#endif
347
348
349
350
351#define CONFIG_UEC_ETH
352#define CONFIG_ETHPRIME "UEC0"
353
354#define CONFIG_UEC_ETH1
355
356#ifdef CONFIG_UEC_ETH1
357#define CONFIG_SYS_UEC1_UCC_NUM 2
358#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
359#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
360#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
361#define CONFIG_SYS_UEC1_PHY_ADDR 3
362#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
363#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
364#endif
365
366#define CONFIG_UEC_ETH2
367
368#ifdef CONFIG_UEC_ETH2
369#define CONFIG_SYS_UEC2_UCC_NUM 3
370#define CONFIG_SYS_UEC2_RX_CLK QE_CLK7
371#define CONFIG_SYS_UEC2_TX_CLK QE_CLK8
372#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
373#define CONFIG_SYS_UEC2_PHY_ADDR 4
374#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
375#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
376#endif
377
378
379
380
381#ifndef CONFIG_SYS_RAMBOOT
382 #define CONFIG_ENV_IS_IN_FLASH 1
383 #define CONFIG_ENV_ADDR \
384 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
385 #define CONFIG_ENV_SECT_SIZE 0x20000
386 #define CONFIG_ENV_SIZE 0x2000
387#else
388 #define CONFIG_ENV_IS_NOWHERE 1
389 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
390 #define CONFIG_ENV_SIZE 0x2000
391#endif
392
393#define CONFIG_LOADS_ECHO 1
394#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
395
396
397
398
399#define CONFIG_BOOTP_BOOTFILESIZE
400#define CONFIG_BOOTP_BOOTPATH
401#define CONFIG_BOOTP_GATEWAY
402#define CONFIG_BOOTP_HOSTNAME
403
404
405
406
407
408#if defined(CONFIG_PCI)
409 #define CONFIG_CMD_PCI
410#endif
411
412#undef CONFIG_WATCHDOG
413
414
415
416
417#define CONFIG_SYS_LONGHELP
418#define CONFIG_SYS_LOAD_ADDR 0x2000000
419
420#if defined(CONFIG_CMD_KGDB)
421 #define CONFIG_SYS_CBSIZE 1024
422#else
423 #define CONFIG_SYS_CBSIZE 256
424#endif
425
426
427#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
428#define CONFIG_SYS_MAXARGS 16
429
430#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
431
432
433
434
435
436
437
438#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
439#define CONFIG_SYS_BOOTM_LEN (64 << 20)
440
441
442
443
444#define CONFIG_SYS_HID0_INIT 0x000000000
445#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
446 HID0_ENABLE_INSTRUCTION_CACHE)
447#define CONFIG_SYS_HID2 HID2_HBE
448
449
450
451
452
453#define CONFIG_HIGH_BATS 1
454
455
456#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
457 | BATL_PP_RW \
458 | BATL_MEMCOHERENCE)
459#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
460 | BATU_BL_256M \
461 | BATU_VS \
462 | BATU_VP)
463#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
464#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
465
466
467#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
468 | BATL_PP_RW \
469 | BATL_CACHEINHIBIT \
470 | BATL_GUARDEDSTORAGE)
471#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
472 | BATU_BL_4M \
473 | BATU_VS \
474 | BATU_VP)
475#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
476#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
477
478
479#define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \
480 | BATL_PP_RW \
481 | BATL_CACHEINHIBIT \
482 | BATL_GUARDEDSTORAGE)
483#define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \
484 | BATU_BL_128K \
485 | BATU_VS \
486 | BATU_VP)
487#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
488#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
489
490
491#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \
492 | BATL_PP_RW \
493 | BATL_MEMCOHERENCE)
494#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \
495 | BATU_BL_32M \
496 | BATU_VS \
497 | BATU_VP)
498#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \
499 | BATL_PP_RW \
500 | BATL_CACHEINHIBIT \
501 | BATL_GUARDEDSTORAGE)
502#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
503
504#define CONFIG_SYS_IBAT4L (0)
505#define CONFIG_SYS_IBAT4U (0)
506#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
507#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
508
509
510#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
511#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
512 | BATU_BL_128K \
513 | BATU_VS \
514 | BATU_VP)
515#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
516#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
517
518#ifdef CONFIG_PCI
519
520#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \
521 | BATL_PP_RW \
522 | BATL_MEMCOHERENCE)
523#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \
524 | BATU_BL_256M \
525 | BATU_VS \
526 | BATU_VP)
527#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
528#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
529
530#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \
531 | BATL_PP_RW \
532 | BATL_CACHEINHIBIT \
533 | BATL_GUARDEDSTORAGE)
534#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \
535 | BATU_BL_256M \
536 | BATU_VS \
537 | BATU_VP)
538#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
539#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
540#else
541#define CONFIG_SYS_IBAT6L (0)
542#define CONFIG_SYS_IBAT6U (0)
543#define CONFIG_SYS_IBAT7L (0)
544#define CONFIG_SYS_IBAT7U (0)
545#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
546#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
547#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
548#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
549#endif
550
551#if defined(CONFIG_CMD_KGDB)
552#define CONFIG_KGDB_BAUDRATE 230400
553#endif
554
555
556
557 #define CONFIG_ENV_OVERWRITE
558
559#if defined(CONFIG_UEC_ETH)
560#define CONFIG_HAS_ETH0
561#define CONFIG_HAS_ETH1
562#endif
563
564#define CONFIG_LOADADDR 800000
565
566#undef CONFIG_BOOTARGS
567
568#define CONFIG_EXTRA_ENV_SETTINGS \
569 "netdev=eth0\0" \
570 "consoledev=ttyS0\0" \
571 "ramdiskaddr=1000000\0" \
572 "ramdiskfile=ramfs.83xx\0" \
573 "fdtaddr=780000\0" \
574 "fdtfile=mpc832x_mds.dtb\0" \
575 ""
576
577#define CONFIG_NFSBOOTCOMMAND \
578 "setenv bootargs root=/dev/nfs rw " \
579 "nfsroot=$serverip:$rootpath " \
580 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
581 "$netdev:off " \
582 "console=$consoledev,$baudrate $othbootargs;" \
583 "tftp $loadaddr $bootfile;" \
584 "tftp $fdtaddr $fdtfile;" \
585 "bootm $loadaddr - $fdtaddr"
586
587#define CONFIG_RAMBOOTCOMMAND \
588 "setenv bootargs root=/dev/ram rw " \
589 "console=$consoledev,$baudrate $othbootargs;" \
590 "tftp $ramdiskaddr $ramdiskfile;" \
591 "tftp $loadaddr $bootfile;" \
592 "tftp $fdtaddr $fdtfile;" \
593 "bootm $loadaddr $ramdiskaddr $fdtaddr"
594
595#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
596
597#endif
598