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39
40#ifndef __CONFIG_H
41#define __CONFIG_H
42
43#if (CONFIG_SYS_TEXT_BASE == 0xFE000000)
44#define CONFIG_SYS_LOWBOOT
45#endif
46
47
48
49
50#define CONFIG_MPC834x
51#define CONFIG_MPC8349
52
53#ifndef CONFIG_SYS_TEXT_BASE
54#define CONFIG_SYS_TEXT_BASE 0xFEF00000
55#endif
56
57#define CONFIG_SYS_IMMR 0xE0000000
58
59#define CONFIG_MISC_INIT_F
60#define CONFIG_MISC_INIT_R
61
62
63
64
65
66#ifdef CONFIG_MPC8349ITX
67
68#define CONFIG_COMPACT_FLASH
69#define CONFIG_VSC7385_ENET
70#define CONFIG_SATA_SIL3114
71#define CONFIG_SYS_USB_HOST
72#endif
73
74#define CONFIG_RTC_DS1337
75#define CONFIG_SYS_I2C
76#define CONFIG_TSEC_ENET
77
78
79
80
81
82
83#ifdef CONFIG_SYS_I2C
84#define CONFIG_SYS_I2C_FSL
85#define CONFIG_SYS_FSL_I2C_SPEED 400000
86#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
87#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
88#define CONFIG_SYS_FSL_I2C2_SPEED 400000
89#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
90#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
91
92#define CONFIG_SYS_SPD_BUS_NUM 1
93#define CONFIG_SYS_RTC_BUS_NUM 1
94
95#define CONFIG_SYS_I2C_8574_ADDR1 0x20
96#define CONFIG_SYS_I2C_8574_ADDR2 0x21
97#define CONFIG_SYS_I2C_8574A_ADDR1 0x38
98#define CONFIG_SYS_I2C_8574A_ADDR2 0x39
99#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
100#define CONFIG_SYS_I2C_RTC_ADDR 0x68
101#define SPD_EEPROM_ADDRESS 0x51
102
103
104#define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
105 {1, CONFIG_SYS_I2C_8574_ADDR2}, \
106 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
107 {1, CONFIG_SYS_I2C_8574A_ADDR2} }
108
109
110#define I2C_8574_REVISION 0x03
111#define I2C_8574_CF 0x08
112#define I2C_8574_MPCICLKRN 0x10
113#define I2C_8574_PCI66 0x20
114#define I2C_8574_FLASHSIDE 0x40
115
116#endif
117
118
119#ifdef CONFIG_COMPACT_FLASH
120
121#define CONFIG_SYS_IDE_MAXBUS 1
122#define CONFIG_SYS_IDE_MAXDEVICE 1
123
124#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
125#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE
126#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000
127#define CONFIG_SYS_ATA_REG_OFFSET 0
128#define CONFIG_SYS_ATA_ALT_OFFSET 0x0200
129#define CONFIG_SYS_ATA_STRIDE 2
130
131
132#define ATA_RESET_TIME 1
133
134#endif
135
136
137
138
139#ifdef CONFIG_SATA_SIL3114
140
141#define CONFIG_SYS_SATA_MAX_DEVICE 4
142#define CONFIG_LIBATA
143#define CONFIG_LBA48
144
145#endif
146
147#ifdef CONFIG_SYS_USB_HOST
148
149
150
151#define CONFIG_USB_EHCI
152#define CONFIG_USB_EHCI_FSL
153
154
155
156#if 1
157#define CONFIG_HAS_FSL_MPH_USB
158#else
159#define CONFIG_HAS_FSL_DR_USB
160#endif
161
162#endif
163
164
165
166
167#define CONFIG_SYS_DDR_BASE 0x00000000
168#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
169#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
170#define CONFIG_SYS_83XX_DDR_USES_CS0
171#define CONFIG_SYS_MEMTEST_START 0x1000
172#define CONFIG_SYS_MEMTEST_END 0x2000
173
174#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
175 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
176
177#define CONFIG_VERY_BIG_RAM
178#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20)
179
180#ifdef CONFIG_SYS_I2C
181#define CONFIG_SPD_EEPROM
182#endif
183
184
185#ifndef CONFIG_SPD_EEPROM
186 #define CONFIG_SYS_DDR_SIZE 256
187 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
188 | CSCONFIG_ROW_BIT_13 \
189 | CSCONFIG_COL_BIT_10)
190
191 #define CONFIG_SYS_DDR_TIMING_1 0x26242321
192 #define CONFIG_SYS_DDR_TIMING_2 0x00000800
193#endif
194
195
196
197
198
199#define CONFIG_SYS_FLASH_CFI
200#define CONFIG_FLASH_CFI_DRIVER
201#define CONFIG_SYS_FLASH_BASE 0xFE000000
202#define CONFIG_SYS_FLASH_EMPTY_INFO
203
204#define CONFIG_SYS_MAX_FLASH_SECT 135
205#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
206#define CONFIG_SYS_FLASH_WRITE_TOUT 500
207#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
208
209
210
211#define CONFIG_SYS_FLASH_QUIET_TEST
212#define CONFIG_SYS_MAX_FLASH_BANKS 2
213#define CONFIG_SYS_FLASH_BANKS_LIST \
214 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
215#define CONFIG_SYS_FLASH_SIZE 16
216#define CONFIG_SYS_FLASH_PROTECTION 1
217
218
219
220#ifdef CONFIG_VSC7385_ENET
221
222#define CONFIG_TSEC2
223
224
225#define CONFIG_VSC7385_IMAGE 0xFEFFE000
226#define CONFIG_VSC7385_IMAGE_SIZE 8192
227
228#endif
229
230
231
232
233
234
235
236#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
237 | BR_PS_16 \
238 | BR_MS_GPCM \
239 | BR_V)
240#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
241 | OR_UPM_XAM \
242 | OR_GPCM_CSNT \
243 | OR_GPCM_ACS_DIV2 \
244 | OR_GPCM_XACS \
245 | OR_GPCM_SCY_15 \
246 | OR_GPCM_TRLX_SET \
247 | OR_GPCM_EHTR_SET \
248 | OR_GPCM_EAD)
249#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
250#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB)
251
252
253
254#define CONFIG_SYS_VSC7385_BASE 0xF8000000
255
256#ifdef CONFIG_VSC7385_ENET
257
258#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \
259 | BR_PS_8 \
260 | BR_MS_GPCM \
261 | BR_V)
262#define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \
263 | OR_GPCM_CSNT \
264 | OR_GPCM_XACS \
265 | OR_GPCM_SCY_15 \
266 | OR_GPCM_SETA \
267 | OR_GPCM_TRLX_SET \
268 | OR_GPCM_EHTR_SET \
269 | OR_GPCM_EAD)
270
271#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE
272#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
273
274#endif
275
276
277
278#define CONFIG_SYS_LED_BASE 0xF9000000
279#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \
280 | BR_PS_8 \
281 | BR_MS_GPCM \
282 | BR_V)
283#define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \
284 | OR_GPCM_CSNT \
285 | OR_GPCM_ACS_DIV2 \
286 | OR_GPCM_XACS \
287 | OR_GPCM_SCY_9 \
288 | OR_GPCM_TRLX_SET \
289 | OR_GPCM_EHTR_SET \
290 | OR_GPCM_EAD)
291
292
293
294#ifdef CONFIG_COMPACT_FLASH
295
296#define CONFIG_SYS_CF_BASE 0xF0000000
297
298#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \
299 | BR_PS_16 \
300 | BR_MS_UPMA \
301 | BR_V)
302#define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI)
303
304#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE
305#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
306
307#endif
308
309
310
311
312#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
313
314#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
315#define CONFIG_SYS_RAMBOOT
316#else
317#undef CONFIG_SYS_RAMBOOT
318#endif
319
320#define CONFIG_SYS_INIT_RAM_LOCK
321#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
322#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
323
324#define CONFIG_SYS_GBL_DATA_OFFSET \
325 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
326#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
327
328
329#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
330#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
331
332
333
334
335
336
337
338#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
339#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
340#define CONFIG_SYS_LBC_LBCR 0x00000000
341
342
343#define CONFIG_SYS_LBC_LSRT 0x32000000
344
345#define CONFIG_SYS_LBC_MRTPR 0x20000000
346
347
348
349
350#define CONFIG_CONS_INDEX 1
351#define CONFIG_SYS_NS16550_SERIAL
352#define CONFIG_SYS_NS16550_REG_SIZE 1
353#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
354
355#define CONFIG_SYS_BAUDRATE_TABLE \
356 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
357
358#define CONSOLE ttyS0
359
360#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
361#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
362
363
364
365
366#ifdef CONFIG_PCI
367#define CONFIG_PCI_INDIRECT_BRIDGE
368
369#define CONFIG_MPC83XX_PCI2
370
371
372
373
374
375#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
376#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
377#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
378#define CONFIG_SYS_PCI1_MMIO_BASE \
379 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
380#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
381#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
382#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
383#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
384#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000
385
386#ifdef CONFIG_MPC83XX_PCI2
387#define CONFIG_SYS_PCI2_MEM_BASE \
388 (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
389#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
390#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000
391#define CONFIG_SYS_PCI2_MMIO_BASE \
392 (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
393#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
394#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000
395#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
396#define CONFIG_SYS_PCI2_IO_PHYS \
397 (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
398#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000
399#endif
400
401#ifndef CONFIG_PCI_PNP
402 #define PCI_ENET0_IOADDR 0x00000000
403 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE
404 #define PCI_IDSEL_NUMBER 0x0f
405#endif
406
407#define CONFIG_PCI_SCAN_SHOW
408
409#endif
410
411#define CONFIG_PCI_66M
412#ifdef CONFIG_PCI_66M
413#define CONFIG_83XX_CLKIN 66666666
414#else
415#define CONFIG_83XX_CLKIN 33333333
416#endif
417
418
419
420#ifdef CONFIG_TSEC_ENET
421
422#define CONFIG_MII
423#define CONFIG_PHY_GIGE
424
425#define CONFIG_TSEC1
426
427#ifdef CONFIG_TSEC1
428#define CONFIG_HAS_ETH0
429#define CONFIG_TSEC1_NAME "TSEC0"
430#define CONFIG_SYS_TSEC1_OFFSET 0x24000
431#define TSEC1_PHY_ADDR 0x1c
432#define TSEC1_PHYIDX 0
433#define TSEC1_FLAGS TSEC_GIGABIT
434#endif
435
436#ifdef CONFIG_TSEC2
437#define CONFIG_HAS_ETH1
438#define CONFIG_TSEC2_NAME "TSEC1"
439#define CONFIG_SYS_TSEC2_OFFSET 0x25000
440
441#define TSEC2_PHY_ADDR 4
442#define TSEC2_PHYIDX 0
443#define TSEC2_FLAGS TSEC_GIGABIT
444#endif
445
446#define CONFIG_ETHPRIME "Freescale TSEC"
447
448#endif
449
450
451
452
453#define CONFIG_ENV_OVERWRITE
454
455#ifndef CONFIG_SYS_RAMBOOT
456 #define CONFIG_ENV_IS_IN_FLASH
457 #define CONFIG_ENV_ADDR \
458 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
459 #define CONFIG_ENV_SECT_SIZE 0x10000
460 #define CONFIG_ENV_SIZE 0x2000
461#else
462 #undef CONFIG_FLASH_CFI_DRIVER
463 #define CONFIG_ENV_IS_NOWHERE
464 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
465 #define CONFIG_ENV_SIZE 0x2000
466#endif
467
468#define CONFIG_LOADS_ECHO
469#define CONFIG_SYS_LOADS_BAUD_CHANGE
470
471
472
473
474#define CONFIG_BOOTP_BOOTFILESIZE
475#define CONFIG_BOOTP_BOOTPATH
476#define CONFIG_BOOTP_GATEWAY
477#define CONFIG_BOOTP_HOSTNAME
478
479
480
481
482#define CONFIG_CMD_IRQ
483#define CONFIG_CMD_SDRAM
484
485#if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \
486 || defined(CONFIG_USB_STORAGE)
487 #define CONFIG_SUPPORT_VFAT
488#endif
489
490#ifdef CONFIG_COMPACT_FLASH
491 #define CONFIG_CMD_IDE
492#endif
493
494#ifdef CONFIG_SATA_SIL3114
495 #define CONFIG_CMD_SATA
496#endif
497
498#if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE)
499#endif
500
501#ifdef CONFIG_PCI
502 #define CONFIG_CMD_PCI
503#endif
504
505
506#undef CONFIG_WATCHDOG
507
508
509
510
511#define CONFIG_SYS_LONGHELP
512#define CONFIG_CMDLINE_EDITING
513#define CONFIG_AUTO_COMPLETE
514
515#define CONFIG_SYS_LOAD_ADDR 0x2000000
516#define CONFIG_LOADADDR 800000
517
518#if defined(CONFIG_CMD_KGDB)
519 #define CONFIG_SYS_CBSIZE 1024
520#else
521 #define CONFIG_SYS_CBSIZE 256
522#endif
523
524
525#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
526#define CONFIG_SYS_MAXARGS 16
527
528#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
529
530
531
532
533
534
535
536#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
537#define CONFIG_SYS_BOOTM_LEN (64 << 20)
538
539#define CONFIG_SYS_HRCW_LOW (\
540 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
541 HRCWL_DDR_TO_SCB_CLK_1X1 |\
542 HRCWL_CSB_TO_CLKIN_4X1 |\
543 HRCWL_VCO_1X2 |\
544 HRCWL_CORE_TO_CSB_2X1)
545
546#ifdef CONFIG_SYS_LOWBOOT
547#define CONFIG_SYS_HRCW_HIGH (\
548 HRCWH_PCI_HOST |\
549 HRCWH_32_BIT_PCI |\
550 HRCWH_PCI1_ARBITER_ENABLE |\
551 HRCWH_PCI2_ARBITER_ENABLE |\
552 HRCWH_CORE_ENABLE |\
553 HRCWH_FROM_0X00000100 |\
554 HRCWH_BOOTSEQ_DISABLE |\
555 HRCWH_SW_WATCHDOG_DISABLE |\
556 HRCWH_ROM_LOC_LOCAL_16BIT |\
557 HRCWH_TSEC1M_IN_GMII |\
558 HRCWH_TSEC2M_IN_GMII)
559#else
560#define CONFIG_SYS_HRCW_HIGH (\
561 HRCWH_PCI_HOST |\
562 HRCWH_32_BIT_PCI |\
563 HRCWH_PCI1_ARBITER_ENABLE |\
564 HRCWH_PCI2_ARBITER_ENABLE |\
565 HRCWH_CORE_ENABLE |\
566 HRCWH_FROM_0XFFF00100 |\
567 HRCWH_BOOTSEQ_DISABLE |\
568 HRCWH_SW_WATCHDOG_DISABLE |\
569 HRCWH_ROM_LOC_LOCAL_16BIT |\
570 HRCWH_TSEC1M_IN_GMII |\
571 HRCWH_TSEC2M_IN_GMII)
572#endif
573
574
575
576
577#define CONFIG_SYS_ACR_PIPE_DEP 3
578#define CONFIG_SYS_ACR_RPTCNT 3
579#define CONFIG_SYS_SPCR_TSEC1EP 3
580#define CONFIG_SYS_SPCR_TSEC2EP 3
581#define CONFIG_SYS_SCCR_TSEC1CM 1
582#define CONFIG_SYS_SCCR_TSEC2CM 1
583#define CONFIG_SYS_SCCR_USBMPHCM 3
584#define CONFIG_SYS_SCCR_USBDRCM 0
585
586
587
588
589
590#define CONFIG_SYS_SICRH SICRH_TSOBI1
591
592#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1)
593
594#define CONFIG_SYS_HID0_INIT 0x00000000
595#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE
596
597#define CONFIG_SYS_HID2 HID2_HBE
598#define CONFIG_HIGH_BATS 1
599
600
601#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
602 | BATL_PP_RW \
603 | BATL_MEMCOHERENCE)
604#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
605 | BATU_BL_256M \
606 | BATU_VS \
607 | BATU_VP)
608
609
610#ifdef CONFIG_PCI
611#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
612 | BATL_PP_RW \
613 | BATL_MEMCOHERENCE)
614#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
615 | BATU_BL_256M \
616 | BATU_VS \
617 | BATU_VP)
618#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
619 | BATL_PP_RW \
620 | BATL_CACHEINHIBIT \
621 | BATL_GUARDEDSTORAGE)
622#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
623 | BATU_BL_256M \
624 | BATU_VS \
625 | BATU_VP)
626#else
627#define CONFIG_SYS_IBAT1L 0
628#define CONFIG_SYS_IBAT1U 0
629#define CONFIG_SYS_IBAT2L 0
630#define CONFIG_SYS_IBAT2U 0
631#endif
632
633#ifdef CONFIG_MPC83XX_PCI2
634#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
635 | BATL_PP_RW \
636 | BATL_MEMCOHERENCE)
637#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
638 | BATU_BL_256M \
639 | BATU_VS \
640 | BATU_VP)
641#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
642 | BATL_PP_RW \
643 | BATL_CACHEINHIBIT \
644 | BATL_GUARDEDSTORAGE)
645#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
646 | BATU_BL_256M \
647 | BATU_VS \
648 | BATU_VP)
649#else
650#define CONFIG_SYS_IBAT3L 0
651#define CONFIG_SYS_IBAT3U 0
652#define CONFIG_SYS_IBAT4L 0
653#define CONFIG_SYS_IBAT4U 0
654#endif
655
656
657#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
658 | BATL_PP_RW \
659 | BATL_CACHEINHIBIT \
660 | BATL_GUARDEDSTORAGE)
661#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
662 | BATU_BL_256M \
663 | BATU_VS \
664 | BATU_VP)
665
666
667#define CONFIG_SYS_IBAT6L (0xF0000000 \
668 | BATL_PP_RW \
669 | BATL_MEMCOHERENCE \
670 | BATL_GUARDEDSTORAGE)
671#define CONFIG_SYS_IBAT6U (0xF0000000 \
672 | BATU_BL_256M \
673 | BATU_VS \
674 | BATU_VP)
675
676#define CONFIG_SYS_IBAT7L 0
677#define CONFIG_SYS_IBAT7U 0
678
679#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
680#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
681#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
682#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
683#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
684#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
685#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
686#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
687#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
688#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
689#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
690#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
691#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
692#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
693#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
694#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
695
696#if defined(CONFIG_CMD_KGDB)
697#define CONFIG_KGDB_BAUDRATE 230400
698#endif
699
700
701
702
703#define CONFIG_ENV_OVERWRITE
704
705#define CONFIG_NETDEV "eth0"
706
707#ifdef CONFIG_MPC8349ITX
708#define CONFIG_HOSTNAME "mpc8349emitx"
709#else
710#define CONFIG_HOSTNAME "mpc8349emitxgp"
711#endif
712
713
714#define CONFIG_ROOTPATH "/nfsroot/rootfs"
715#define CONFIG_BOOTFILE "uImage"
716
717#define CONFIG_UBOOTPATH "u-boot.bin"
718
719#ifdef CONFIG_MPC8349ITX
720#define CONFIG_FDTFILE "mpc8349emitx.dtb"
721#else
722#define CONFIG_FDTFILE "mpc8349emitxgp.dtb"
723#endif
724
725
726#define CONFIG_BOOTARGS \
727 "root=/dev/nfs rw" \
728 " nfsroot=" __stringify(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH \
729 " ip=" __stringify(CONFIG_IPADDR) ":" \
730 __stringify(CONFIG_SERVERIP) ":" \
731 __stringify(CONFIG_GATEWAYIP) ":" \
732 __stringify(CONFIG_NETMASK) ":" \
733 CONFIG_HOSTNAME ":" CONFIG_NETDEV ":off" \
734 " console=" __stringify(CONSOLE) "," __stringify(CONFIG_BAUDRATE)
735
736#define CONFIG_EXTRA_ENV_SETTINGS \
737 "console=" __stringify(CONSOLE) "\0" \
738 "netdev=" CONFIG_NETDEV "\0" \
739 "uboot=" CONFIG_UBOOTPATH "\0" \
740 "tftpflash=tftpboot $loadaddr $uboot; " \
741 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
742 " +$filesize; " \
743 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
744 " +$filesize; " \
745 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
746 " $filesize; " \
747 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
748 " +$filesize; " \
749 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
750 " $filesize\0" \
751 "fdtaddr=780000\0" \
752 "fdtfile=" CONFIG_FDTFILE "\0"
753
754#define CONFIG_NFSBOOTCOMMAND \
755 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \
756 " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
757 " console=$console,$baudrate $othbootargs; " \
758 "tftp $loadaddr $bootfile;" \
759 "tftp $fdtaddr $fdtfile;" \
760 "bootm $loadaddr - $fdtaddr"
761
762#define CONFIG_RAMBOOTCOMMAND \
763 "setenv bootargs root=/dev/ram rw" \
764 " console=$console,$baudrate $othbootargs; " \
765 "tftp $ramdiskaddr $ramdiskfile;" \
766 "tftp $loadaddr $bootfile;" \
767 "tftp $fdtaddr $fdtfile;" \
768 "bootm $loadaddr $ramdiskaddr $fdtaddr"
769
770#endif
771