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13#ifndef __CONFIG_H
14#define __CONFIG_H
15
16#ifndef CONFIG_SYS_TEXT_BASE
17#define CONFIG_SYS_TEXT_BASE 0xfff80000
18#endif
19
20#define CONFIG_SYS_SRIO
21#define CONFIG_SRIO1
22
23#define CONFIG_PCI1
24#define CONFIG_PCIE1
25#undef CONFIG_PCI2
26#define CONFIG_FSL_PCI_INIT 1
27#define CONFIG_PCI_INDIRECT_BRIDGE 1
28#define CONFIG_FSL_PCIE_RESET 1
29#define CONFIG_SYS_PCI_64BIT 1
30
31#define CONFIG_TSEC_ENET
32#define CONFIG_ENV_OVERWRITE
33#define CONFIG_INTERRUPTS
34
35#define CONFIG_FSL_VIA
36
37#ifndef __ASSEMBLY__
38extern unsigned long get_clock_freq(void);
39#endif
40#define CONFIG_SYS_CLK_FREQ get_clock_freq()
41
42
43
44
45#define CONFIG_L2_CACHE
46#define CONFIG_BTB
47
48
49
50
51#define CONFIG_ENABLE_36BIT_PHYS 1
52
53#ifdef CONFIG_PHYS_64BIT
54#define CONFIG_ADDR_MAP
55#define CONFIG_SYS_NUM_ADDR_MAP 16
56#endif
57
58#define CONFIG_SYS_MEMTEST_START 0x00200000
59#define CONFIG_SYS_MEMTEST_END 0x00400000
60
61#define CONFIG_SYS_CCSRBAR 0xe0000000
62#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
63
64
65#undef CONFIG_FSL_DDR_INTERACTIVE
66#define CONFIG_SPD_EEPROM
67#define CONFIG_DDR_SPD
68
69#define CONFIG_DDR_ECC
70#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
71#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
72
73#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
74#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
75
76#define CONFIG_DIMM_SLOTS_PER_CTLR 1
77#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
78
79
80#define SPD_EEPROM_ADDRESS 0x51
81
82
83#ifndef CONFIG_SPD_EEPROM
84#error ("CONFIG_SPD_EEPROM is required")
85#endif
86
87#undef CONFIG_CLOCKS_IN_MHZ
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152
153#define CONFIG_SYS_FLASH_BASE 0xff000000
154#ifdef CONFIG_PHYS_64BIT
155#define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull
156#else
157#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
158#endif
159
160#define CONFIG_SYS_BR0_PRELIM \
161 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V)
162#define CONFIG_SYS_BR1_PRELIM \
163 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
164
165#define CONFIG_SYS_OR0_PRELIM 0xff806e65
166#define CONFIG_SYS_OR1_PRELIM 0xff806e65
167
168#define CONFIG_SYS_FLASH_BANKS_LIST \
169 {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
170#define CONFIG_SYS_MAX_FLASH_BANKS 2
171#define CONFIG_SYS_MAX_FLASH_SECT 128
172#undef CONFIG_SYS_FLASH_CHECKSUM
173#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
174#define CONFIG_SYS_FLASH_WRITE_TOUT 500
175
176#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
177
178#define CONFIG_FLASH_CFI_DRIVER
179#define CONFIG_SYS_FLASH_CFI
180#define CONFIG_SYS_FLASH_EMPTY_INFO
181
182#define CONFIG_HWCONFIG
183
184
185
186
187#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000
188#ifdef CONFIG_PHYS_64BIT
189#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull
190#else
191#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE
192#endif
193#define CONFIG_SYS_LBC_SDRAM_SIZE 64
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213#define CONFIG_SYS_BR2_PRELIM \
214 (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \
215 | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V)
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231#define CONFIG_SYS_OR2_PRELIM 0xfc006901
232
233#define CONFIG_SYS_LBC_LCRR 0x00030004
234#define CONFIG_SYS_LBC_LBCR 0x00000000
235#define CONFIG_SYS_LBC_LSRT 0x20000000
236#define CONFIG_SYS_LBC_MRTPR 0x00000000
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243
244#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
245 | LSDMR_PRETOACT7 \
246 | LSDMR_ACTTORW7 \
247 | LSDMR_BL8 \
248 | LSDMR_WRC4 \
249 | LSDMR_CL3 \
250 | LSDMR_RFEN \
251 )
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283#define CONFIG_FSL_CADMUS
284
285#define CADMUS_BASE_ADDR 0xf8000000
286#ifdef CONFIG_PHYS_64BIT
287#define CADMUS_BASE_ADDR_PHYS 0xff8000000ull
288#else
289#define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR
290#endif
291#define CONFIG_SYS_BR3_PRELIM \
292 (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V)
293#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
294
295#define CONFIG_SYS_INIT_RAM_LOCK 1
296#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000
297#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
298
299#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
300#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
301
302#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
303#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
304
305
306#define CONFIG_CONS_INDEX 2
307#define CONFIG_SYS_NS16550_SERIAL
308#define CONFIG_SYS_NS16550_REG_SIZE 1
309#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
310
311#define CONFIG_SYS_BAUDRATE_TABLE \
312 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
313
314#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
315#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
316
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319
320#define CONFIG_SYS_I2C
321#define CONFIG_SYS_I2C_FSL
322#define CONFIG_SYS_FSL_I2C_SPEED 400000
323#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
324#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
325#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
326
327
328#define CONFIG_ID_EEPROM
329#define CONFIG_SYS_I2C_EEPROM_CCID
330#define CONFIG_SYS_ID_EEPROM
331#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
332#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
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337
338#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
339#ifdef CONFIG_PHYS_64BIT
340#define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000
341#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
342#else
343#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
344#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
345#endif
346#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000
347#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
348#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
349#ifdef CONFIG_PHYS_64BIT
350#define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull
351#else
352#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
353#endif
354#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000
355
356#ifdef CONFIG_PCIE1
357#define CONFIG_SYS_PCIE1_NAME "Slot"
358#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
359#ifdef CONFIG_PHYS_64BIT
360#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
361#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull
362#else
363#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
364#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
365#endif
366#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
367#define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000
368#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
369#ifdef CONFIG_PHYS_64BIT
370#define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull
371#else
372#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
373#endif
374#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000
375#endif
376
377
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379
380#define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000
381#ifdef CONFIG_PHYS_64BIT
382#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull
383#else
384#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000
385#endif
386#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000
387
388#ifdef CONFIG_LEGACY
389#define BRIDGE_ID 17
390#define VIA_ID 2
391#else
392#define BRIDGE_ID 28
393#define VIA_ID 4
394#endif
395
396#if defined(CONFIG_PCI)
397#undef CONFIG_EEPRO100
398#undef CONFIG_TULIP
399
400#define CONFIG_PCI_SCAN_SHOW
401
402#endif
403
404#if defined(CONFIG_TSEC_ENET)
405
406#define CONFIG_MII 1
407#define CONFIG_TSEC1 1
408#define CONFIG_TSEC1_NAME "eTSEC0"
409#define CONFIG_TSEC2 1
410#define CONFIG_TSEC2_NAME "eTSEC1"
411#define CONFIG_TSEC3 1
412#define CONFIG_TSEC3_NAME "eTSEC2"
413#define CONFIG_TSEC4
414#define CONFIG_TSEC4_NAME "eTSEC3"
415#undef CONFIG_MPC85XX_FEC
416
417#define CONFIG_PHY_MARVELL
418
419#define TSEC1_PHY_ADDR 0
420#define TSEC2_PHY_ADDR 1
421#define TSEC3_PHY_ADDR 2
422#define TSEC4_PHY_ADDR 3
423
424#define TSEC1_PHYIDX 0
425#define TSEC2_PHYIDX 0
426#define TSEC3_PHYIDX 0
427#define TSEC4_PHYIDX 0
428#define TSEC1_FLAGS TSEC_GIGABIT
429#define TSEC2_FLAGS TSEC_GIGABIT
430#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
431#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
432
433
434#define CONFIG_ETHPRIME "eTSEC0"
435#define CONFIG_PHY_GIGE 1
436#endif
437
438
439
440
441#define CONFIG_ENV_IS_IN_FLASH 1
442#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
443#define CONFIG_ENV_ADDR 0xfff80000
444#else
445#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
446#endif
447#define CONFIG_ENV_SECT_SIZE 0x20000
448#define CONFIG_ENV_SIZE 0x2000
449
450#define CONFIG_LOADS_ECHO 1
451#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
452
453
454
455
456#define CONFIG_BOOTP_BOOTFILESIZE
457#define CONFIG_BOOTP_BOOTPATH
458#define CONFIG_BOOTP_GATEWAY
459#define CONFIG_BOOTP_HOSTNAME
460
461
462
463
464#define CONFIG_CMD_IRQ
465#define CONFIG_CMD_REGINFO
466
467#if defined(CONFIG_PCI)
468 #define CONFIG_CMD_PCI
469#endif
470
471#undef CONFIG_WATCHDOG
472
473
474
475
476#define CONFIG_SYS_LONGHELP
477#define CONFIG_CMDLINE_EDITING
478#define CONFIG_AUTO_COMPLETE
479#define CONFIG_SYS_LOAD_ADDR 0x2000000
480#if defined(CONFIG_CMD_KGDB)
481#define CONFIG_SYS_CBSIZE 1024
482#else
483#define CONFIG_SYS_CBSIZE 256
484#endif
485#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
486#define CONFIG_SYS_MAXARGS 16
487#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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494#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
495#define CONFIG_SYS_BOOTM_LEN (64 << 20)
496
497#if defined(CONFIG_CMD_KGDB)
498#define CONFIG_KGDB_BAUDRATE 230400
499#endif
500
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503
504#if defined(CONFIG_TSEC_ENET)
505#define CONFIG_HAS_ETH0
506#define CONFIG_HAS_ETH1
507#define CONFIG_HAS_ETH2
508#define CONFIG_HAS_ETH3
509#endif
510
511#define CONFIG_IPADDR 192.168.1.253
512
513#define CONFIG_HOSTNAME unknown
514#define CONFIG_ROOTPATH "/nfsroot"
515#define CONFIG_BOOTFILE "8548cds/uImage.uboot"
516#define CONFIG_UBOOTPATH 8548cds/u-boot.bin
517
518#define CONFIG_SERVERIP 192.168.1.1
519#define CONFIG_GATEWAYIP 192.168.1.1
520#define CONFIG_NETMASK 255.255.255.0
521
522#define CONFIG_LOADADDR 1000000
523
524#undef CONFIG_BOOTARGS
525
526#define CONFIG_EXTRA_ENV_SETTINGS \
527 "hwconfig=fsl_ddr:ecc=off\0" \
528 "netdev=eth0\0" \
529 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
530 "tftpflash=tftpboot $loadaddr $uboot; " \
531 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
532 " +$filesize; " \
533 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
534 " +$filesize; " \
535 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
536 " $filesize; " \
537 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
538 " +$filesize; " \
539 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
540 " $filesize\0" \
541 "consoledev=ttyS1\0" \
542 "ramdiskaddr=2000000\0" \
543 "ramdiskfile=ramdisk.uboot\0" \
544 "fdtaddr=1e00000\0" \
545 "fdtfile=mpc8548cds.dtb\0"
546
547#define CONFIG_NFSBOOTCOMMAND \
548 "setenv bootargs root=/dev/nfs rw " \
549 "nfsroot=$serverip:$rootpath " \
550 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
551 "console=$consoledev,$baudrate $othbootargs;" \
552 "tftp $loadaddr $bootfile;" \
553 "tftp $fdtaddr $fdtfile;" \
554 "bootm $loadaddr - $fdtaddr"
555
556#define CONFIG_RAMBOOTCOMMAND \
557 "setenv bootargs root=/dev/ram rw " \
558 "console=$consoledev,$baudrate $othbootargs;" \
559 "tftp $ramdiskaddr $ramdiskfile;" \
560 "tftp $loadaddr $bootfile;" \
561 "tftp $fdtaddr $fdtfile;" \
562 "bootm $loadaddr $ramdiskaddr $fdtaddr"
563
564#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
565
566#endif
567