1/* 2 * (C) Copyright 2003 3 * Denis Peter d.peter@mpl.ch 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* 9 * File: PATI.h 10 */ 11 12#ifndef __CONFIG_H 13#define __CONFIG_H 14 15/* 16 * High Level Configuration Options 17 */ 18 19#define CONFIG_MPC555 1 /* This is an MPC555 CPU */ 20#define CONFIG_PATI 1 /* ...On a PATI board */ 21 22#define CONFIG_SYS_TEXT_BASE 0xFFF00000 23 24/* Serial Console Configuration */ 25#define CONFIG_5xx_CONS_SCI1 26#undef CONFIG_5xx_CONS_SCI2 27 28/* 29 * BOOTP options 30 */ 31#define CONFIG_BOOTP_BOOTFILESIZE 32#define CONFIG_BOOTP_BOOTPATH 33#define CONFIG_BOOTP_GATEWAY 34#define CONFIG_BOOTP_HOSTNAME 35 36/* 37 * Command line configuration. 38 */ 39#define CONFIG_CMD_REGINFO 40#define CONFIG_CMD_REGINFO 41#define CONFIG_CMD_EEPROM 42#define CONFIG_CMD_IRQ 43 44#define CONFIG_BOOTCOMMAND "" /* autoboot command */ 45 46#define CONFIG_BOOTARGS "" /* */ 47 48#define CONFIG_WATCHDOG /* turn on platform specific watchdog */ 49 50#define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */ 51 52/* 53 * Miscellaneous configurable options 54 */ 55#define CONFIG_PREBOOT 56 57#define CONFIG_SYS_LONGHELP /* undef to save memory */ 58#if defined(CONFIG_CMD_KGDB) 59#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 60#else 61#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 62#endif 63#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 64#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 65#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 66 67#define CONFIG_SYS_MEMTEST_START 0x00010000 /* memtest works on */ 68#define CONFIG_SYS_MEMTEST_END 0x00A00000 /* 10 MB in SRAM */ 69 70#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 71 72#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 } 73 74/*********************************************************************** 75 * Last Stage Init 76 ***********************************************************************/ 77#define CONFIG_LAST_STAGE_INIT 78 79/* 80 * Low Level Configuration Settings 81 */ 82 83/* 84 * Internal Memory Mapped (This is not the IMMR content) 85 */ 86#define CONFIG_SYS_IMMR 0x01C00000 /* Physical start adress of internal memory map */ 87 88/* 89 * Definitions for initial stack pointer and data area 90 */ 91#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */ 92#define CONFIG_SYS_INIT_RAM_SIZE (CONFIG_SYS_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */ 93#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_RAM_ADDR) - GENERATED_GBL_DATA_SIZE) /* Offset from the beginning of ram */ 94#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_IMMR + 0x03fa000) /* Physical start adress of inital stack */ 95/* 96 * Start addresses for the final memory configuration 97 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 98 */ 99#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */ 100#define CONFIG_SYS_FLASH_BASE 0xffC00000 /* External flash */ 101#define PCI_BASE 0x03000000 /* PCI Base (CS2) */ 102#define PCI_CONFIG_BASE 0x04000000 /* PCI & PLD (CS3) */ 103#define PLD_CONFIG_BASE 0x04001000 /* PLD (CS3) */ 104 105#define CONFIG_SYS_MONITOR_BASE 0xFFF00000 106/* CONFIG_SYS_FLASH_BASE */ /* CONFIG_SYS_TEXT_BASE is defined in the board config.mk file. */ 107 /* This adress is given to the linker with -Ttext to */ 108 /* locate the text section at this adress. */ 109#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 192 kB for Monitor */ 110#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 111 112#define CONFIG_SYS_RESET_ADDRESS (PLD_CONFIG_BASE + 0x10) /* Adress which causes reset */ 113 114/* 115 * For booting Linux, the board info and command line data 116 * have to be in the first 8 MB of memory, since this is 117 * the maximum mapped by the Linux kernel during initialization. 118 */ 119#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 120 121/*----------------------------------------------------------------------- 122 * FLASH organization 123 *----------------------------------------------------------------------- 124 * 125 */ 126 127#define CONFIG_SYS_FLASH_PROTECTION 128#define CONFIG_SYS_FLASH_EMPTY_INFO 129 130#define CONFIG_SYS_FLASH_CFI 131#define CONFIG_FLASH_CFI_DRIVER 132 133#define CONFIG_FLASH_SHOW_PROGRESS 45 134 135#define CONFIG_SYS_MAX_FLASH_BANKS 1 136#define CONFIG_SYS_MAX_FLASH_SECT 128 137 138#define CONFIG_ENV_IS_IN_EEPROM 139#ifdef CONFIG_ENV_IS_IN_EEPROM 140#define CONFIG_ENV_OFFSET 0 141#define CONFIG_ENV_SIZE 2048 142#endif 143 144#undef CONFIG_ENV_IS_IN_FLASH 145#ifdef CONFIG_ENV_IS_IN_FLASH 146#define CONFIG_ENV_SIZE 0x00002000 /* Set whole sector as env */ 147#define CONFIG_ENV_OFFSET ((0 - CONFIG_SYS_FLASH_BASE) - CONFIG_ENV_SIZE) /* Environment starts at this adress */ 148#endif 149 150#define CONFIG_SPI 1 151#define CONFIG_SYS_SPI_CS_USED 0x09 /* CS0 and CS3 are used */ 152#define CONFIG_SYS_SPI_CS_BASE 0x08 /* CS3 is active low */ 153#define CONFIG_SYS_SPI_CS_ACT 0x00 /* CS3 is active low */ 154/*----------------------------------------------------------------------- 155 * SYPCR - System Protection Control 156 * SYPCR can only be written once after reset! 157 *----------------------------------------------------------------------- 158 * SW Watchdog freeze 159 */ 160#undef CONFIG_WATCHDOG 161#if defined(CONFIG_WATCHDOG) 162#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 163 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 164#else 165#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 166 SYPCR_SWP) 167#endif /* CONFIG_WATCHDOG */ 168 169/*----------------------------------------------------------------------- 170 * TBSCR - Time Base Status and Control 171 *----------------------------------------------------------------------- 172 * Clear Reference Interrupt Status, Timebase freezing enabled 173 */ 174#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 175 176/*----------------------------------------------------------------------- 177 * PISCR - Periodic Interrupt Status and Control 178 *----------------------------------------------------------------------- 179 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 180 */ 181#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 182 183/*----------------------------------------------------------------------- 184 * SCCR - System Clock and reset Control Register 185 *----------------------------------------------------------------------- 186 * Set clock output, timebase and RTC source and divider, 187 * power management and some other internal clocks 188 */ 189#define SCCR_MASK SCCR_EBDF00 190#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \ 191 SCCR_COM01 | SCCR_DFNL000 | SCCR_DFNH000) 192 193/*----------------------------------------------------------------------- 194 * SIUMCR - SIU Module Configuration 195 *----------------------------------------------------------------------- 196 * Data show cycle 197 */ 198#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */ 199 200/*----------------------------------------------------------------------- 201 * PLPRCR - PLL, Low-Power, and Reset Control Register 202 *----------------------------------------------------------------------- 203 * Set all bits to 40 Mhz 204 * 205 */ 206#define CONFIG_SYS_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */ 207 208#define CONFIG_SYS_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0) 209 210/*----------------------------------------------------------------------- 211 * UMCR - UIMB Module Configuration Register 212 *----------------------------------------------------------------------- 213 * 214 */ 215#define CONFIG_SYS_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */ 216 217/*----------------------------------------------------------------------- 218 * ICTRL - I-Bus Support Control Register 219 */ 220#define CONFIG_SYS_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */ 221 222/*----------------------------------------------------------------------- 223 * USIU - Memory Controller Register 224 *----------------------------------------------------------------------- 225 */ 226#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA) 227#define CONFIG_SYS_OR0_PRELIM (0xffc00000) /* SCY is not used if external TA is set */ 228/* SDRAM */ 229#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA) 230#define CONFIG_SYS_OR1_PRELIM (OR_ADDR_MK_FF) /* SCY is not used if external TA is set */ 231/* PCI */ 232#define CONFIG_SYS_BR2_PRELIM (PCI_BASE | BR_V | BR_PS_32 | BR_SETA) 233#define CONFIG_SYS_OR2_PRELIM (OR_ADDR_MK_FF) 234/* config registers: */ 235#define CONFIG_SYS_BR3_PRELIM (PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA) 236#define CONFIG_SYS_OR3_PRELIM (0xffff0000) 237 238#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* We don't realign the flash */ 239 240/*----------------------------------------------------------------------- 241 * DER - Timer Decrementer 242 *----------------------------------------------------------------------- 243 * Initialise to zero 244 */ 245#define CONFIG_SYS_DER 0x00000000 246 247#endif /* __CONFIG_H */ 248