LXR uboot/include/configs/PMC405DE.h

   1/*
   2 * (C) Copyright 2009
   3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd.eu
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8#ifndef __CONFIG_H
   9#define __CONFIG_H
  10
  11#define CONFIG_405EP            1       /* This is a PPC405 CPU         */
  12#define CONFIG_PMC405DE         1       /* ...on a PMC405DE board       */
  13
  14#define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  15
  16#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  17#define CONFIG_BOARD_TYPES      1       /* support board types          */
  18
  19#define CONFIG_SYS_CLK_FREQ     33330000 /* external frequency to pll   */
  20
  21#undef  CONFIG_BOOTARGS
  22#undef  CONFIG_BOOTCOMMAND
  23
  24#define CONFIG_PREBOOT                  /* enable preboot variable      */
  25
  26#define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change*/
  27
  28#define CONFIG_HAS_ETH1
  29
  30#define CONFIG_PPC4xx_EMAC
  31#define CONFIG_MII              1       /* MII PHY management           */
  32#define CONFIG_PHY_ADDR         1       /* PHY address                  */
  33#define CONFIG_PHY1_ADDR        2       /* 2nd PHY address              */
  34
  35#define CONFIG_SYS_RX_ETH_BUFFER        16 /* use 16 rx buffer on 405 emac */
  36
  37/*
  38 * BOOTP options
  39 */
  40#define CONFIG_BOOTP_SUBNETMASK
  41#define CONFIG_BOOTP_GATEWAY
  42#define CONFIG_BOOTP_HOSTNAME
  43#define CONFIG_BOOTP_BOOTPATH
  44#define CONFIG_BOOTP_DNS
  45#define CONFIG_BOOTP_DNS2
  46#define CONFIG_BOOTP_SEND_HOSTNAME
  47
  48/*
  49 * Command line configuration.
  50 */
  51#define CONFIG_CMD_EEPROM
  52#define CONFIG_CMD_IRQ
  53#define CONFIG_CMD_PCI
  54
  55#undef  CONFIG_WATCHDOG                 /* watchdog disabled */
  56#define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0 */
  57#define CONFIG_PRAM             0
  58
  59/*
  60 * Miscellaneous configurable options
  61 */
  62#define CONFIG_SYS_LONGHELP
  63
  64#define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
  65#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  66#define CONFIG_SYS_MAXARGS      16              /* max number of command args */
  67#define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
  68
  69#define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device */
  70
  71#define CONFIG_SYS_MEMTEST_START        0x0100000 /* memtest works on */
  72#define CONFIG_SYS_MEMTEST_END          0x3000000 /* 1 ... 48 MB in DRAM */
  73
  74#define CONFIG_CONS_INDEX       2       /* Use UART1                    */
  75#define CONFIG_SYS_NS16550_SERIAL
  76#define CONFIG_SYS_NS16550_REG_SIZE     1
  77#define CONFIG_SYS_NS16550_CLK          get_serial_clock()
  78
  79#undef  CONFIG_SYS_EXT_SERIAL_CLOCK
  80#define CONFIG_SYS_BASE_BAUD            691200
  81
  82#define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
  83#define CONFIG_SYS_EXTBDINFO    1       /* To use extended board_into (bd_t) */
  84
  85#define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
  86#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
  87
  88/*
  89 * PCI stuff
  90 */
  91#define PCI_HOST_ADAPTER        0       /* configure as pci adapter     */
  92#define PCI_HOST_FORCE          1       /* configure as pci host        */
  93#define PCI_HOST_AUTO           2       /* detected via arbiter enable  */
  94
  95#define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
  96#define CONFIG_PCI_HOST PCI_HOST_AUTO  /* select pci host function      */
  97
  98#define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup          */
  99
 100/*
 101 * PCI identification
 102 */
 103#define CONFIG_SYS_PCI_SUBSYS_VENDORID          PCI_VENDOR_ID_ESDGMBH
 104#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x040e /* Dev ID: Non-Monarch */
 105#define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x040f /* Dev ID: Monarch */
 106#define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH     PCI_CLASS_PROCESSOR_POWERPC
 107#define CONFIG_SYS_PCI_CLASSCODE_MONARCH        PCI_CLASS_BRIDGE_HOST
 108
 109#define CONFIG_SYS_PCI_CLASSCODE CONFIG_SYS_PCI_CLASSCODE_MONARCH
 110#define CONFIG_SYS_PCI_SUBSYS_DEVICEID CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
 111
 112#define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram */
 113#define CONFIG_SYS_PCI_PTM1MS  0xfc000001      /* 64MB, enable=1 */
 114#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address */
 115#define CONFIG_SYS_PCI_PTM2LA  0xef000000      /* point to CPLD, GPIO */
 116#define CONFIG_SYS_PCI_PTM2MS  0xff000001      /* 16MB, enable=1 */
 117#define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address */
 118
 119#define CONFIG_PCI_4xx_PTM_OVERWRITE    1 /* overwrite PTMx settings by env */
 120
 121/*
 122 * For booting Linux, the board info and command line data
 123 * have to be in the first 8 MB of memory, since this is
 124 * the maximum mapped by the Linux kernel during initialization.
 125 */
 126#define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 127/*
 128 * FLASH organization
 129 */
 130#define CONFIG_SYS_FLASH_CFI            1       /* CFI compatible */
 131#define CONFIG_FLASH_CFI_DRIVER         1       /* Use common CFI driver */
 132
 133#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 134
 135#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max. no. memory banks */
 136#define CONFIG_SYS_MAX_FLASH_SECT       512     /* max sectors per chip */
 137
 138#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* erase timeout (in ms) */
 139#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* write timeout (in ms) */
 140
 141#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* buffered writes (faster) */
 142#define CONFIG_SYS_FLASH_PROTECTION     1       /* hardware flash protection */
 143
 144#define CONFIG_SYS_FLASH_EMPTY_INFO     1 /* 'E' for empty sector (flinfo) */
 145#define CONFIG_SYS_FLASH_QUIET_TEST     1 /* don't warn upon unknown flash */
 146
 147/*
 148 * Start addresses for the final memory configuration
 149 * (Set up by the startup code)
 150 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 151 */
 152#define CONFIG_SYS_SDRAM_BASE           0x00000000
 153#define CONFIG_SYS_FLASH_BASE           0xfe000000
 154#define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 155#define CONFIG_SYS_MONITOR_LEN          (~(CONFIG_SYS_TEXT_BASE) + 1)
 156#define CONFIG_SYS_MALLOC_LEN           (256 * 1024)
 157
 158/*
 159 * Environment in EEPROM setup
 160 */
 161#define CONFIG_ENV_IS_IN_EEPROM         1
 162#define CONFIG_ENV_OFFSET               0x100
 163#define CONFIG_ENV_SIZE                 0x700
 164
 165/*
 166 * I2C EEPROM (24W16) for environment
 167 */
 168#define CONFIG_SYS_I2C
 169#define CONFIG_SYS_I2C_PPC4XX
 170#define CONFIG_SYS_I2C_PPC4XX_CH0
 171#define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 172#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 173
 174#define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM 24W16 */
 175#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address */
 176/* mask of address bits that overflow into the "EEPROM chip address" */
 177#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 178#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24WC08 has */
 179                                        /* 16 byte page write mode using*/
 180                                        /* last 4 bits of the address */
 181#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10 /* and takes up to 10 msec */
 182#define CONFIG_SYS_EEPROM_WREN          1
 183
 184#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x50
 185#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET     0x40
 186#define CONFIG_4xx_CONFIG_BLOCKSIZE             0x20
 187
 188/*
 189 * RTC
 190 */
 191#define CONFIG_RTC_RX8025
 192
 193/*
 194 * External Bus Controller (EBC) Setup
 195 * (max. 55MHZ EBC clock)
 196 */
 197/* Memory Bank 0 (NOR flash) BAS=0xFE0,BS=32MB,BU=R/W,BW=16bit */
 198#define CONFIG_SYS_EBC_PB0AP            0x03017200
 199#define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_FLASH_BASE | 0xba000)
 200
 201/* Memory Bank 1 (CPLD) BAS=0xEF0,BS=16MB,BU=R/W,BW=16bit */
 202#define CONFIG_SYS_CPLD_BASE            0xef000000
 203#define CONFIG_SYS_EBC_PB1AP            0x00800000
 204#define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_CPLD_BASE | 0x18000)
 205
 206/*
 207 * Definitions for initial stack pointer and data area (in data cache)
 208 */
 209/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 210#define CONFIG_SYS_TEMP_STACK_OCM         1
 211
 212/* On Chip Memory location */
 213#define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 214#define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 215/* inside SDRAM */
 216#define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR
 217/* End of used area in RAM */
 218#define CONFIG_SYS_INIT_RAM_SIZE                CONFIG_SYS_OCM_DATA_SIZE
 219
 220#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 221                                         GENERATED_GBL_DATA_SIZE)
 222#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 223
 224/*
 225 * GPIO Configuration
 226 */
 227#define CONFIG_SYS_4xx_GPIO_TABLE {                  /* GPIO    Alt1       */ \
 228{                                                                             \
 229/* GPIO Core 0 */                                                             \
 230{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO0   PerBLast   */ \
 231{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1   TS1E       */ \
 232{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2   TS2E       */ \
 233{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3   TS1O       */ \
 234{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4   TS2O       */ \
 235{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1 },      /* GPIO5   TS3        */ \
 236{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1 },      /* GPIO6   TS4        */ \
 237{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1 },      /* GPIO7   TS5        */ \
 238{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8   TS6        */ \
 239{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1 },      /* GPIO9   TrcClk     */ \
 240{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10  PerCS1     */ \
 241{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO11  PerCS2     */ \
 242{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO12  PerCS3     */ \
 243{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO13  PerCS4     */ \
 244{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO14  PerAddr03  */ \
 245{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO15  PerAddr04  */ \
 246{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16  PerAddr05  */ \
 247{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17  IRQ0       */ \
 248{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18  IRQ1       */ \
 249{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19  IRQ2       */ \
 250{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20  IRQ3       */ \
 251{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21  IRQ4       */ \
 252{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22  IRQ5       */ \
 253{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO23  IRQ6       */ \
 254{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24  UART0_DCD  */ \
 255{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO25  UART0_DSR  */ \
 256{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO26  UART0_RI   */ \
 257{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO27  UART0_DTR  */ \
 258{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28  UART1_Rx   */ \
 259{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29  UART1_Tx   */ \
 260{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30  RejectPkt0 */ \
 261{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31  RejectPkt1 */ \
 262}                                                                             \
 263}
 264
 265#define CONFIG_SYS_GPIO_HWREV_MASK      (0xf0000000 >> 1)       /* GPIO1..4 */
 266#define CONFIG_SYS_GPIO_HWREV_SHIFT     27
 267#define CONFIG_SYS_GPIO_LEDRUN_N        (0x80000000 >> 5)       /* GPIO5 */
 268#define CONFIG_SYS_GPIO_LEDA_N          (0x80000000 >> 6)       /* GPIO6 */
 269#define CONFIG_SYS_GPIO_LEDB_N          (0x80000000 >> 7)       /* GPIO7 */
 270#define CONFIG_SYS_GPIO_SELFRST_N       (0x80000000 >> 8)       /* GPIO8 */
 271#define CONFIG_SYS_GPIO_EEPROM_WP       (0x80000000 >> 9)       /* GPIO9 */
 272#define CONFIG_SYS_GPIO_MONARCH_N       (0x80000000 >> 11)      /* GPIO11 */
 273#define CONFIG_SYS_GPIO_EREADY          (0x80000000 >> 12)      /* GPIO12 */
 274#define CONFIG_SYS_GPIO_M66EN           (0x80000000 >> 13)      /* GPIO13 */
 275
 276/*
 277 * Default speed selection (cpu_plb_opb_ebc) in mhz.
 278 * This value will be set if iic boot eprom is disabled.
 279 */
 280#undef CONFIG_SYS_FCPU333MHZ
 281#define CONFIG_SYS_FCPU266MHZ
 282#undef CONFIG_SYS_FCPU133MHZ
 283
 284#if defined(CONFIG_SYS_FCPU333MHZ)
 285/*
 286 * CPU: 333MHz
 287 * PLB/SDRAM/MAL: 111MHz
 288 * OPB: 55MHz
 289 * EBC: 55MHz
 290 * PCI: 55MHz (111MHz on M66EN=1)
 291 */
 292#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_3 |           \
 293                        PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |        \
 294                        PLL_MALDIV_1 | PLL_PCIDIV_2)
 295#define PLLMR1_DEFAULT (PLL_FBKDIV_10  |                        \
 296                        PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |         \
 297                        PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
 298#endif
 299
 300#if defined(CONFIG_SYS_FCPU266MHZ)
 301/*
 302 * CPU: 266MHz
 303 * PLB/SDRAM/MAL: 133MHz
 304 * OPB: 66MHz
 305 * EBC: 44MHz
 306 * PCI: 44MHz (66MHz on M66EN=1)
 307 */
 308#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_2 |           \
 309                        PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |        \
 310                        PLL_MALDIV_1 | PLL_PCIDIV_3)
 311#define PLLMR1_DEFAULT (PLL_FBKDIV_8  |  \
 312                        PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |         \
 313                        PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 314#endif
 315
 316#if defined(CONFIG_SYS_FCPU133MHZ)
 317/*
 318 * CPU: 133MHz
 319 * PLB/SDRAM/MAL: 133MHz
 320 * OPB: 66MHz
 321 * EBC: 44MHz
 322 * PCI: 44MHz (66MHz on M66EN=1)
 323 */
 324#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_1 |           \
 325                        PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |        \
 326                        PLL_MALDIV_1 | PLL_PCIDIV_3)
 327#define PLLMR1_DEFAULT (PLL_FBKDIV_4  |  \
 328                        PLL_FWDDIVA_6 | PLL_FWDDIVB_6 |         \
 329                        PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 330#endif
 331
 332#endif /* __CONFIG_H */
 333