LXR uboot/include/configs/PMC440.h

   1/*
   2 * (C) Copyright 2007-2008
   3 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
   4 * Based on the sequoia configuration file.
   5 *
   6 * (C) Copyright 2006-2007
   7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
   8 *
   9 * (C) Copyright 2006
  10 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
  11 * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
  12 *
  13 * SPDX-License-Identifier:     GPL-2.0+
  14 */
  15
  16/************************************************************************
  17 * PMC440.h - configuration for esd PMC440 boards
  18 ***********************************************************************/
  19#ifndef __CONFIG_H
  20#define __CONFIG_H
  21
  22/*-----------------------------------------------------------------------
  23 * High Level Configuration Options
  24 *----------------------------------------------------------------------*/
  25#define CONFIG_440EPX           1       /* Specific PPC440EPx   */
  26#define CONFIG_440              1       /* ... PPC440 family    */
  27
  28#ifndef CONFIG_SYS_TEXT_BASE
  29#define CONFIG_SYS_TEXT_BASE    0xFFF90000
  30#endif
  31
  32#define CONFIG_SYS_CLK_FREQ     33333400
  33
  34#if 0 /* temporary disabled because OS/9 does not like dcache on startup */
  35#define CONFIG_4xx_DCACHE               /* enable dcache        */
  36#endif
  37
  38#define CONFIG_MISC_INIT_F      1
  39#define CONFIG_MISC_INIT_R      1       /* Call misc_init_r     */
  40#define CONFIG_BOARD_TYPES      1       /* support board types  */
  41/*-----------------------------------------------------------------------
  42 * Base addresses -- Note these are effective addresses where the
  43 * actual resources get mapped (not physical addresses)
  44 *----------------------------------------------------------------------*/
  45#define CONFIG_SYS_MONITOR_LEN          (~(CONFIG_SYS_TEXT_BASE) + 1)
  46#define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserve 256 kB for malloc()  */
  47
  48#define CONFIG_PRAM             0       /* use pram variable to overwrite */
  49
  50#define CONFIG_SYS_BOOT_BASE_ADDR       0xf0000000
  51#define CONFIG_SYS_SDRAM_BASE           0x00000000      /* _must_ be 0          */
  52#define CONFIG_SYS_FLASH_BASE           0xfc000000      /* start of FLASH       */
  53#define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
  54#define CONFIG_SYS_NAND_ADDR            0xd0000000      /* NAND Flash           */
  55#define CONFIG_SYS_OCM_BASE             0xe0010000      /* ocm                  */
  56#define CONFIG_SYS_OCM_DATA_ADDR        CONFIG_SYS_OCM_BASE
  57#define CONFIG_SYS_PCI_BASE             0xe0000000      /* Internal PCI regs    */
  58#define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped pci memory    */
  59#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE  + 0x10000000
  60#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
  61#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
  62#define CONFIG_SYS_PCI_MEMSIZE          0x80000000      /* 2GB! */
  63
  64#define CONFIG_SYS_USB2D0_BASE          0xe0000100
  65#define CONFIG_SYS_USB_DEVICE           0xe0000000
  66#define CONFIG_SYS_USB_HOST             0xe0000400
  67#define CONFIG_SYS_FPGA_BASE0           0xef000000      /* 32 bit */
  68#define CONFIG_SYS_FPGA_BASE1           0xef100000      /* 16 bit */
  69#define CONFIG_SYS_RESET_BASE           0xef200000
  70
  71/*-----------------------------------------------------------------------
  72 * Initial RAM & stack pointer
  73 *----------------------------------------------------------------------*/
  74/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache     */
  75#define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_BASE     /* OCM                  */
  76#define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)
  77#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  78#define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
  79
  80/*-----------------------------------------------------------------------
  81 * Serial Port
  82 *----------------------------------------------------------------------*/
  83#define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  84#define CONFIG_SYS_NS16550_SERIAL
  85#define CONFIG_SYS_NS16550_REG_SIZE     1
  86#define CONFIG_SYS_NS16550_CLK          get_serial_clock()
  87#undef CONFIG_SYS_EXT_SERIAL_CLOCK
  88
  89#define CONFIG_SYS_BAUDRATE_TABLE                                               \
  90        {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  91
  92/*-----------------------------------------------------------------------
  93 * Environment
  94 *----------------------------------------------------------------------*/
  95#define CONFIG_ENV_IS_IN_EEPROM 1       /* use FLASH for environment vars */
  96
  97/*-----------------------------------------------------------------------
  98 * RTC
  99 *----------------------------------------------------------------------*/
 100#define CONFIG_RTC_RX8025
 101
 102/*-----------------------------------------------------------------------
 103 * FLASH related
 104 *----------------------------------------------------------------------*/
 105#define CONFIG_SYS_FLASH_CFI            /* The flash is CFI compatible  */
 106#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver        */
 107
 108#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 109
 110#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 111#define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
 112
 113#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 114#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 115
 116#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 117#define CONFIG_SYS_FLASH_PROTECTION     1       /* use hardware flash protection        */
 118
 119#define CONFIG_SYS_FLASH_EMPTY_INFO     /* print 'E' for empty sector on flinfo */
 120#define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash        */
 121
 122#ifdef CONFIG_ENV_IS_IN_FLASH
 123#define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector          */
 124#define CONFIG_ENV_ADDR         ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 125#define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector     */
 126
 127/* Address and size of Redundant Environment Sector     */
 128#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 129#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 130#endif
 131
 132#ifdef CONFIG_ENV_IS_IN_EEPROM
 133#define CONFIG_I2C_ENV_EEPROM_BUS       0
 134#define CONFIG_ENV_OFFSET               0       /* environment starts at the beginning of the EEPROM */
 135#define CONFIG_ENV_SIZE         0x1000  /* 4096 bytes may be used for env vars */
 136#endif
 137
 138/*-----------------------------------------------------------------------
 139 * DDR SDRAM
 140 *----------------------------------------------------------------------*/
 141#define CONFIG_DDR_DATA_EYE     /* use DDR2 optimization        */
 142#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
 143                                                  /* 440EPx errata CHIP 11 */
 144
 145/*-----------------------------------------------------------------------
 146 * I2C
 147 *----------------------------------------------------------------------*/
 148#define CONFIG_SYS_I2C
 149#define CONFIG_SYS_I2C_PPC4XX
 150#define CONFIG_SYS_I2C_PPC4XX_CH0
 151#define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 152#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 153#define CONFIG_SYS_I2C_PPC4XX_CH1
 154#define CONFIG_SYS_I2C_PPC4XX_SPEED_1           400000
 155#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1           0x7F
 156
 157#define CONFIG_SYS_I2C_EEPROM_ADDR              0x54
 158#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 159#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5
 160#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 161#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x01
 162
 163#define CONFIG_SYS_EEPROM_WREN                  1
 164#define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR 0x52
 165
 166/*
 167 * standard dtt sensor configuration - bottom bit will determine local or
 168 * remote sensor of the TMP401
 169 */
 170#define CONFIG_DTT_SENSORS              { 0, 1 }
 171
 172/*
 173 * The PMC440 uses a TI TMP401 temperature sensor. This part
 174 * is basically compatible to the ADM1021 that is supported
 175 * by U-Boot.
 176 *
 177 * - i2c addr 0x4c
 178 * - conversion rate 0x02 = 0.25 conversions/second
 179 * - ALERT ouput disabled
 180 * - local temp sensor enabled, min set to 0 deg, max set to 70 deg
 181 * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
 182 */
 183#define CONFIG_DTT_ADM1021
 184#define CONFIG_SYS_DTT_ADM1021          { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
 185
 186#define CONFIG_PREBOOT          "echo Add \\\"run fpga\\\" and "        \
 187                                "\\\"painit\\\" to preboot command"
 188
 189#undef  CONFIG_BOOTARGS
 190
 191/* Setup some board specific values for the default environment variables */
 192#define CONFIG_HOSTNAME         pmc440
 193#define CONFIG_SYS_BOOTFILE     "bootfile=/tftpboot/pmc440/uImage\0"
 194#define CONFIG_SYS_ROOTPATH     "rootpath=/opt/eldk/ppc_4xxFP\0"
 195
 196#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 197        CONFIG_SYS_BOOTFILE                                             \
 198        CONFIG_SYS_ROOTPATH                                             \
 199        "fdt_file=/tftpboot/pmc440/pmc440.dtb\0"                        \
 200        "netdev=eth0\0"                                                 \
 201        "ethrotate=no\0"                                                \
 202        "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 203        "nfsroot=${serverip}:${rootpath}\0"                             \
 204        "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 205        "addip=setenv bootargs ${bootargs} "                            \
 206                "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 207                ":${hostname}:${netdev}:off panic=1\0"                  \
 208        "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
 209        "addmisc=setenv bootargs ${bootargs} mem=${mem}\0"              \
 210        "nandargs=setenv bootargs root=/dev/mtdblock6 rootfstype=jffs2 rw\0" \
 211        "nand_boot_fdt=run nandargs addip addtty addmisc;"              \
 212                "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 213        "net_nfs_fdt=tftp ${kernel_addr_r} ${bootfile};"                \
 214                "tftp  ${fdt_addr_r} ${fdt_file};"                      \
 215                "run nfsargs addip addtty addmisc;"                     \
 216                "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 217        "kernel_addr=ffc00000\0"                                        \
 218        "kernel_addr_r=200000\0"                                        \
 219        "fpga_addr=fff00000\0"                                          \
 220        "fdt_addr=fff80000\0"                                           \
 221        "fdt_addr_r=800000\0"                                           \
 222        "fpga=fpga loadb 0 ${fpga_addr}\0"                              \
 223        "load=tftp 200000 /tftpboot/pmc440/u-boot.bin\0"                \
 224        "update=protect off fff90000 ffffffff;era fff90000 ffffffff;"   \
 225                "cp.b 200000 fff90000 70000\0"                          \
 226        ""
 227
 228
 229#define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 230#define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 231
 232#define CONFIG_PPC4xx_EMAC
 233#define CONFIG_IBM_EMAC4_V4     1
 234#define CONFIG_MII              1       /* MII PHY management           */
 235#define CONFIG_PHY_ADDR         0       /* PHY address, See schematics  */
 236
 237#define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 238
 239#define CONFIG_HAS_ETH0
 240#define CONFIG_SYS_RX_ETH_BUFFER        32      /* Number of ethernet rx buffers & descriptors */
 241
 242#define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 243#define CONFIG_PHY1_ADDR        1
 244#define CONFIG_RESET_PHY_R      1
 245
 246/* USB */
 247#define CONFIG_USB_OHCI_NEW
 248#define CONFIG_SYS_OHCI_BE_CONTROLLER
 249
 250#define CONFIG_SYS_USB_OHCI_BOARD_INIT 1
 251#define CONFIG_SYS_USB_OHCI_CPU_INIT    1
 252#define CONFIG_SYS_USB_OHCI_REGS_BASE   CONFIG_SYS_USB_HOST
 253#define CONFIG_SYS_USB_OHCI_SLOT_NAME   "ppc440"
 254#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 255
 256/* Comment this out to enable USB 1.1 device */
 257#define USB_2_0_DEVICE
 258
 259/* Partitions */
 260
 261#define CONFIG_CMD_DTT
 262#define CONFIG_CMD_EEPROM
 263#define CONFIG_CMD_NAND
 264#define CONFIG_CMD_PCI
 265#define CONFIG_CMD_REGINFO
 266
 267/* POST support */
 268#define CONFIG_POST             (CONFIG_SYS_POST_MEMORY |       \
 269                                 CONFIG_SYS_POST_CPU    |       \
 270                                 CONFIG_SYS_POST_UART   |       \
 271                                 CONFIG_SYS_POST_I2C    |       \
 272                                 CONFIG_SYS_POST_CACHE  |       \
 273                                 CONFIG_SYS_POST_FPU    |       \
 274                                 CONFIG_SYS_POST_ETHER  |       \
 275                                 CONFIG_SYS_POST_SPR)
 276
 277#define CONFIG_LOGBUFFER
 278#define CONFIG_SYS_POST_CACHE_ADDR      0x7fff0000      /* free virtual address     */
 279
 280#define CONFIG_SUPPORT_VFAT
 281
 282/*-----------------------------------------------------------------------
 283 * Miscellaneous configurable options
 284 *----------------------------------------------------------------------*/
 285#define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 286#if defined(CONFIG_CMD_KGDB)
 287#define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 288#else
 289#define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 290#endif
 291#define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 292#define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 293#define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 294
 295#define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on          */
 296#define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM       */
 297
 298#define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address      */
 299#define CONFIG_SYS_EXTBDINFO            1       /* To use extended board_into (bd_t) */
 300
 301#define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 302#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 303
 304/*-----------------------------------------------------------------------
 305 * PCI stuff
 306 *----------------------------------------------------------------------*/
 307/* General PCI */
 308#define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 309#define CONFIG_SYS_PCI_CACHE_LINE_SIZE  0       /* to avoid problems with PNP   */
 310#define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup  */
 311#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
 312
 313/* Board-specific PCI */
 314#define CONFIG_SYS_PCI_TARGET_INIT
 315#define CONFIG_SYS_PCI_MASTER_INIT
 316#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
 317
 318#define CONFIG_PCI_BOOTDELAY 0
 319
 320/* PCI identification */
 321#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE   /* PCI Vendor ID: esd gmbh      */
 322#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x0441      /* PCI Device ID: Non-Monarch */
 323#define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x0440 /* PCI Device ID: Monarch */
 324/* for weak __pci_target_init() */
 325#define CONFIG_SYS_PCI_SUBSYS_ID        CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
 326#define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH     PCI_CLASS_PROCESSOR_POWERPC
 327#define CONFIG_SYS_PCI_CLASSCODE_MONARCH        PCI_CLASS_BRIDGE_HOST
 328
 329/*
 330 * For booting Linux, the board info and command line data
 331 * have to be in the first 8 MB of memory, since this is
 332 * the maximum mapped by the Linux kernel during initialization.
 333 */
 334#define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 335
 336/*-----------------------------------------------------------------------
 337 * FPGA stuff
 338 *----------------------------------------------------------------------*/
 339#define CONFIG_FPGA
 340#define CONFIG_FPGA_XILINX
 341#define CONFIG_FPGA_SPARTAN2
 342#define CONFIG_FPGA_SPARTAN3
 343
 344#define CONFIG_FPGA_COUNT       2
 345/*-----------------------------------------------------------------------
 346 * External Bus Controller (EBC) Setup
 347 *----------------------------------------------------------------------*/
 348
 349/*
 350 * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
 351 */
 352#define CONFIG_SYS_NAND_CS              2       /* NAND chip connected to CSx   */
 353
 354/* Memory Bank 0 (NOR-FLASH) initialization */
 355#define CONFIG_SYS_EBC_PB0AP            0x03017200
 356#define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_FLASH_BASE | 0xda000)
 357
 358/* Memory Bank 2 (NAND-FLASH) initialization */
 359#define CONFIG_SYS_EBC_PB2AP            0x018003c0
 360#define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_NAND_ADDR | 0x1c000)
 361
 362/* Memory Bank 1 (RESET) initialization */
 363#define CONFIG_SYS_EBC_PB1AP            0x7f817200 /* 0x03017200 */
 364#define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_RESET_BASE | 0x1c000)
 365
 366/* Memory Bank 4 (FPGA / 32Bit) initialization */
 367#define CONFIG_SYS_EBC_PB4AP            0x03840f40      /* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */
 368#define CONFIG_SYS_EBC_PB4CR            (CONFIG_SYS_FPGA_BASE0 | 0x1c000)       /* BS=1M,BU=R/W,BW=32bit */
 369
 370/* Memory Bank 5 (FPGA / 16Bit) initialization */
 371#define CONFIG_SYS_EBC_PB5AP            0x03840f40      /* BME=0,TWT=3,CSN=1,TH=0,RE=1,SOR=0,BEM=1 */
 372#define CONFIG_SYS_EBC_PB5CR            (CONFIG_SYS_FPGA_BASE1 | 0x1a000)       /* BS=1M,BU=R/W,BW=16bit */
 373
 374/*-----------------------------------------------------------------------
 375 * NAND FLASH
 376 *----------------------------------------------------------------------*/
 377#define CONFIG_SYS_MAX_NAND_DEVICE      1
 378#define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
 379#define CONFIG_SYS_NAND_SELECT_DEVICE   1 /* nand driver supports mutipl. chips */
 380
 381#if defined(CONFIG_CMD_KGDB)
 382#define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 383#endif
 384
 385#endif /* __CONFIG_H */
 386