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11#ifndef __T1024RDB_H
12#define __T1024RDB_H
13
14
15#define CONFIG_SYS_BOOK3E_HV
16#define CONFIG_MP
17#define CONFIG_ENABLE_36BIT_PHYS
18
19#ifdef CONFIG_PHYS_64BIT
20#define CONFIG_ADDR_MAP 1
21#define CONFIG_SYS_NUM_ADDR_MAP 64
22#endif
23
24#define CONFIG_SYS_FSL_CPC
25#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
26
27#define CONFIG_ENV_OVERWRITE
28
29
30#ifdef CONFIG_ARCH_T1024
31#define CONFIG_DEEP_SLEEP
32#endif
33
34#ifdef CONFIG_RAMBOOT_PBL
35#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
36#define CONFIG_SPL_FLUSH_IMAGE
37#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
38#define CONFIG_SYS_TEXT_BASE 0x30001000
39#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
40#define CONFIG_SPL_PAD_TO 0x40000
41#define CONFIG_SPL_MAX_SIZE 0x28000
42#define RESET_VECTOR_OFFSET 0x27FFC
43#define BOOT_PAGE_OFFSET 0x27000
44#ifdef CONFIG_SPL_BUILD
45#define CONFIG_SPL_SKIP_RELOCATE
46#define CONFIG_SPL_COMMON_INIT_DDR
47#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
48#endif
49
50#ifdef CONFIG_NAND
51#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
52#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
53#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
54#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
55#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
56#if defined(CONFIG_TARGET_T1024RDB)
57#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg
58#elif defined(CONFIG_TARGET_T1023RDB)
59#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg
60#endif
61#define CONFIG_SPL_NAND_BOOT
62#endif
63
64#ifdef CONFIG_SPIFLASH
65#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
66#define CONFIG_SPL_SPI_FLASH_MINIMAL
67#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
68#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
69#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
70#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
71#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
72#ifndef CONFIG_SPL_BUILD
73#define CONFIG_SYS_MPC85XX_NO_RESETVEC
74#endif
75#if defined(CONFIG_TARGET_T1024RDB)
76#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg
77#elif defined(CONFIG_TARGET_T1023RDB)
78#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg
79#endif
80#define CONFIG_SPL_SPI_BOOT
81#endif
82
83#ifdef CONFIG_SDCARD
84#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
85#define CONFIG_SPL_MMC_MINIMAL
86#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
87#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
88#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
89#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
90#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
91#ifndef CONFIG_SPL_BUILD
92#define CONFIG_SYS_MPC85XX_NO_RESETVEC
93#endif
94#if defined(CONFIG_TARGET_T1024RDB)
95#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg
96#elif defined(CONFIG_TARGET_T1023RDB)
97#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg
98#endif
99#define CONFIG_SPL_MMC_BOOT
100#endif
101
102#endif
103
104#ifndef CONFIG_SYS_TEXT_BASE
105#define CONFIG_SYS_TEXT_BASE 0xeff40000
106#endif
107
108#ifndef CONFIG_RESET_VECTOR_ADDRESS
109#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
110#endif
111
112#ifdef CONFIG_MTD_NOR_FLASH
113#define CONFIG_FLASH_CFI_DRIVER
114#define CONFIG_SYS_FLASH_CFI
115#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
116#endif
117
118
119#define CONFIG_SRIO_PCIE_BOOT_MASTER
120
121
122
123
124#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
125#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000
126#ifdef CONFIG_PHYS_64BIT
127#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
128#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
129#else
130#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
131#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
132#endif
133
134
135
136
137#ifdef CONFIG_PHYS_64BIT
138#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
139#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
140#else
141#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
142#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
143#endif
144#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000
145
146#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
147#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001
148
149
150#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
151#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
152#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
153 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
154
155#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
156#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
157 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
158#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
159#endif
160
161#if defined(CONFIG_SPIFLASH)
162#define CONFIG_SYS_EXTRA_ENV_RELOC
163#define CONFIG_ENV_IS_IN_SPI_FLASH
164#define CONFIG_ENV_SPI_BUS 0
165#define CONFIG_ENV_SPI_CS 0
166#define CONFIG_ENV_SPI_MAX_HZ 10000000
167#define CONFIG_ENV_SPI_MODE 0
168#define CONFIG_ENV_SIZE 0x2000
169#define CONFIG_ENV_OFFSET 0x100000
170#if defined(CONFIG_TARGET_T1024RDB)
171#define CONFIG_ENV_SECT_SIZE 0x10000
172#elif defined(CONFIG_TARGET_T1023RDB)
173#define CONFIG_ENV_SECT_SIZE 0x40000
174#endif
175#elif defined(CONFIG_SDCARD)
176#define CONFIG_SYS_EXTRA_ENV_RELOC
177#define CONFIG_ENV_IS_IN_MMC
178#define CONFIG_SYS_MMC_ENV_DEV 0
179#define CONFIG_ENV_SIZE 0x2000
180#define CONFIG_ENV_OFFSET (512 * 0x800)
181#elif defined(CONFIG_NAND)
182#define CONFIG_SYS_EXTRA_ENV_RELOC
183#define CONFIG_ENV_IS_IN_NAND
184#define CONFIG_ENV_SIZE 0x2000
185#if defined(CONFIG_TARGET_T1024RDB)
186#define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
187#elif defined(CONFIG_TARGET_T1023RDB)
188#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
189#endif
190#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
191#define CONFIG_ENV_IS_IN_REMOTE
192#define CONFIG_ENV_ADDR 0xffe20000
193#define CONFIG_ENV_SIZE 0x2000
194#elif defined(CONFIG_ENV_IS_NOWHERE)
195#define CONFIG_ENV_SIZE 0x2000
196#else
197#define CONFIG_ENV_IS_IN_FLASH
198#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
199#define CONFIG_ENV_SIZE 0x2000
200#define CONFIG_ENV_SECT_SIZE 0x20000
201#endif
202
203#ifndef __ASSEMBLY__
204unsigned long get_board_sys_clk(void);
205unsigned long get_board_ddr_clk(void);
206#endif
207
208#define CONFIG_SYS_CLK_FREQ 100000000
209#define CONFIG_DDR_CLK_FREQ 100000000
210
211
212
213
214#define CONFIG_SYS_CACHE_STASHING
215#define CONFIG_BACKSIDE_L2_CACHE
216#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
217#define CONFIG_BTB
218#define CONFIG_DDR_ECC
219#ifdef CONFIG_DDR_ECC
220#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
221#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
222#endif
223
224#define CONFIG_SYS_MEMTEST_START 0x00200000
225#define CONFIG_SYS_MEMTEST_END 0x00400000
226#define CONFIG_SYS_ALT_MEMTEST
227#define CONFIG_PANIC_HANG
228
229
230
231
232#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
233#define CONFIG_SYS_L3_SIZE (256 << 10)
234#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
235#ifdef CONFIG_RAMBOOT_PBL
236#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
237#endif
238#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
239#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
240#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
241#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
242
243#ifdef CONFIG_PHYS_64BIT
244#define CONFIG_SYS_DCSRBAR 0xf0000000
245#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
246#endif
247
248
249#define CONFIG_ID_EEPROM
250#define CONFIG_SYS_I2C_EEPROM_NXID
251#define CONFIG_SYS_EEPROM_BUS_NUM 0
252#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
253#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
254#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
255#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
256
257
258
259
260#define CONFIG_VERY_BIG_RAM
261#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
262#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
263#define CONFIG_DIMM_SLOTS_PER_CTLR 1
264#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
265#define CONFIG_FSL_DDR_INTERACTIVE
266#if defined(CONFIG_TARGET_T1024RDB)
267#define CONFIG_DDR_SPD
268#define CONFIG_SYS_SPD_BUS_NUM 0
269#define SPD_EEPROM_ADDRESS 0x51
270#define CONFIG_SYS_SDRAM_SIZE 4096
271#elif defined(CONFIG_TARGET_T1023RDB)
272#define CONFIG_SYS_DDR_RAW_TIMING
273#define CONFIG_SYS_SDRAM_SIZE 2048
274#endif
275
276
277
278
279#define CONFIG_SYS_FLASH_BASE 0xe8000000
280#ifdef CONFIG_PHYS_64BIT
281#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
282#else
283#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
284#endif
285
286#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
287#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
288 CSPR_PORT_SIZE_16 | \
289 CSPR_MSEL_NOR | \
290 CSPR_V)
291#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
292
293
294#if defined(CONFIG_TARGET_T1024RDB)
295#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
296#elif defined(CONFIG_TARGET_T1023RDB)
297#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \
298 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
299#endif
300#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
301 FTIM0_NOR_TEADC(0x5) | \
302 FTIM0_NOR_TEAHC(0x5))
303#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
304 FTIM1_NOR_TRAD_NOR(0x1A) |\
305 FTIM1_NOR_TSEQRAD_NOR(0x13))
306#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
307 FTIM2_NOR_TCH(0x4) | \
308 FTIM2_NOR_TWPH(0x0E) | \
309 FTIM2_NOR_TWP(0x1c))
310#define CONFIG_SYS_NOR_FTIM3 0x0
311
312#define CONFIG_SYS_FLASH_QUIET_TEST
313#define CONFIG_FLASH_SHOW_PROGRESS 45
314
315#define CONFIG_SYS_MAX_FLASH_BANKS 1
316#define CONFIG_SYS_MAX_FLASH_SECT 1024
317#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
318#define CONFIG_SYS_FLASH_WRITE_TOUT 500
319
320#define CONFIG_SYS_FLASH_EMPTY_INFO
321#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
322
323#ifdef CONFIG_TARGET_T1024RDB
324
325#define CONFIG_SYS_CPLD_BASE 0xffdf0000
326#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
327#define CONFIG_SYS_CSPR2_EXT (0xf)
328#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
329 | CSPR_PORT_SIZE_8 \
330 | CSPR_MSEL_GPCM \
331 | CSPR_V)
332#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
333#define CONFIG_SYS_CSOR2 0x0
334
335
336#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
337 FTIM0_GPCM_TEADC(0x0e) | \
338 FTIM0_GPCM_TEAHC(0x0e))
339#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
340 FTIM1_GPCM_TRAD(0x1f))
341#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
342 FTIM2_GPCM_TCH(0x8) | \
343 FTIM2_GPCM_TWP(0x1f))
344#define CONFIG_SYS_CS2_FTIM3 0x0
345#endif
346
347
348#define CONFIG_NAND_FSL_IFC
349#define CONFIG_SYS_NAND_BASE 0xff800000
350#ifdef CONFIG_PHYS_64BIT
351#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
352#else
353#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
354#endif
355#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
356#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
357 | CSPR_PORT_SIZE_8 \
358 | CSPR_MSEL_NAND \
359 | CSPR_V)
360#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
361
362#if defined(CONFIG_TARGET_T1024RDB)
363#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
364 | CSOR_NAND_ECC_DEC_EN \
365 | CSOR_NAND_ECC_MODE_4 \
366 | CSOR_NAND_RAL_3 \
367 | CSOR_NAND_PGS_4K \
368 | CSOR_NAND_SPRZ_224 \
369 | CSOR_NAND_PB(64))
370#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
371#elif defined(CONFIG_TARGET_T1023RDB)
372#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
373 | CSOR_NAND_ECC_DEC_EN \
374 | CSOR_NAND_ECC_MODE_4 \
375 | CSOR_NAND_RAL_3 \
376 | CSOR_NAND_PGS_2K \
377 | CSOR_NAND_SPRZ_128 \
378 | CSOR_NAND_PB(64))
379#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
380#endif
381
382#define CONFIG_SYS_NAND_ONFI_DETECTION
383
384#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
385 FTIM0_NAND_TWP(0x18) | \
386 FTIM0_NAND_TWCHT(0x07) | \
387 FTIM0_NAND_TWH(0x0a))
388#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
389 FTIM1_NAND_TWBE(0x39) | \
390 FTIM1_NAND_TRR(0x0e) | \
391 FTIM1_NAND_TRP(0x18))
392#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
393 FTIM2_NAND_TREH(0x0a) | \
394 FTIM2_NAND_TWHRE(0x1e))
395#define CONFIG_SYS_NAND_FTIM3 0x0
396
397#define CONFIG_SYS_NAND_DDR_LAW 11
398#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
399#define CONFIG_SYS_MAX_NAND_DEVICE 1
400#define CONFIG_CMD_NAND
401
402#if defined(CONFIG_NAND)
403#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
404#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
405#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
406#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
407#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
408#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
409#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
410#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
411#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
412#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
413#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
414#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
415#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
416#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
417#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
418#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
419#else
420#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
421#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
422#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
423#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
424#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
425#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
426#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
427#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
428#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
429#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
430#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
431#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
432#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
433#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
434#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
435#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
436#endif
437
438#ifdef CONFIG_SPL_BUILD
439#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
440#else
441#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
442#endif
443
444#if defined(CONFIG_RAMBOOT_PBL)
445#define CONFIG_SYS_RAMBOOT
446#endif
447
448#define CONFIG_BOARD_EARLY_INIT_R
449#define CONFIG_MISC_INIT_R
450
451#define CONFIG_HWCONFIG
452
453
454#define CONFIG_L1_INIT_RAM
455#define CONFIG_SYS_INIT_RAM_LOCK
456#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000
457#ifdef CONFIG_PHYS_64BIT
458#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
459#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
460
461#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
462 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
463 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
464#else
465#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000
466#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
467#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
468#endif
469#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
470
471#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
472 GENERATED_GBL_DATA_SIZE)
473#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
474
475#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
476#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
477
478
479#define CONFIG_CONS_INDEX 1
480#define CONFIG_SYS_NS16550_SERIAL
481#define CONFIG_SYS_NS16550_REG_SIZE 1
482#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
483
484#define CONFIG_SYS_BAUDRATE_TABLE \
485 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
486
487#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
488#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
489#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
490#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
491
492
493#undef CONFIG_FSL_DIU_FB
494#ifdef CONFIG_FSL_DIU_FB
495#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
496#define CONFIG_VIDEO_LOGO
497#define CONFIG_VIDEO_BMP_LOGO
498#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
499
500
501
502
503#undef CONFIG_SYS_FLASH_EMPTY_INFO
504#endif
505
506
507#define CONFIG_SYS_I2C
508#define CONFIG_SYS_I2C_FSL
509#define CONFIG_SYS_FSL_I2C_SPEED 50000
510#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
511#define CONFIG_SYS_FSL_I2C2_SPEED 50000
512#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
513#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
514#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
515
516#define I2C_PCA6408_BUS_NUM 1
517#define I2C_PCA6408_ADDR 0x20
518
519
520#define I2C_MUX_CH_DEFAULT 0x8
521
522
523
524
525#define RTC
526#define CONFIG_RTC_DS1337 1
527#define CONFIG_SYS_I2C_RTC_ADDR 0x68
528
529
530
531
532#define CONFIG_SPI_FLASH_BAR
533#define CONFIG_SF_DEFAULT_SPEED 10000000
534#define CONFIG_SF_DEFAULT_MODE 0
535
536
537
538
539
540#define CONFIG_PCIE1
541#define CONFIG_PCIE2
542#define CONFIG_PCIE3
543#ifdef CONFIG_ARCH_T1040
544#define CONFIG_PCIE4
545#endif
546#define CONFIG_FSL_PCI_INIT
547#define CONFIG_SYS_PCI_64BIT
548#define CONFIG_PCI_INDIRECT_BRIDGE
549
550#ifdef CONFIG_PCI
551
552#ifdef CONFIG_PCIE1
553#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
554#ifdef CONFIG_PHYS_64BIT
555#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
556#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
557#else
558#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
559#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
560#endif
561#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
562#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
563#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
564#ifdef CONFIG_PHYS_64BIT
565#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
566#else
567#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
568#endif
569#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
570#endif
571
572
573#ifdef CONFIG_PCIE2
574#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
575#ifdef CONFIG_PHYS_64BIT
576#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
577#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
578#else
579#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
580#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000
581#endif
582#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
583#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
584#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
585#ifdef CONFIG_PHYS_64BIT
586#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
587#else
588#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
589#endif
590#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
591#endif
592
593
594#ifdef CONFIG_PCIE3
595#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
596#ifdef CONFIG_PHYS_64BIT
597#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
598#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
599#else
600#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
601#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
602#endif
603#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000
604#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
605#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
606#ifdef CONFIG_PHYS_64BIT
607#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
608#else
609#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
610#endif
611#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
612#endif
613
614
615#ifdef CONFIG_PCIE4
616#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
617#ifdef CONFIG_PHYS_64BIT
618#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
619#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
620#else
621#define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000
622#define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000
623#endif
624#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000
625#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
626#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
627#ifdef CONFIG_PHYS_64BIT
628#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
629#else
630#define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000
631#endif
632#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000
633#endif
634
635#define CONFIG_PCI_SCAN_SHOW
636#endif
637
638
639
640
641#define CONFIG_HAS_FSL_DR_USB
642
643#ifdef CONFIG_HAS_FSL_DR_USB
644#define CONFIG_USB_EHCI
645#define CONFIG_USB_EHCI_FSL
646#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
647#endif
648
649
650
651
652#ifdef CONFIG_MMC
653#define CONFIG_FSL_ESDHC
654#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
655#endif
656
657
658#ifndef CONFIG_NOBQFMAN
659#define CONFIG_SYS_DPAA_QBMAN
660#define CONFIG_SYS_BMAN_NUM_PORTALS 10
661#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
662#ifdef CONFIG_PHYS_64BIT
663#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
664#else
665#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
666#endif
667#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
668#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
669#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
670#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
671#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
672#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
673 CONFIG_SYS_BMAN_CENA_SIZE)
674#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
675#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
676#define CONFIG_SYS_QMAN_NUM_PORTALS 10
677#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
678#ifdef CONFIG_PHYS_64BIT
679#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
680#else
681#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
682#endif
683#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
684#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
685#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
686#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
687#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
688#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
689 CONFIG_SYS_QMAN_CENA_SIZE)
690#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
691#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
692
693#define CONFIG_SYS_DPAA_FMAN
694
695#ifdef CONFIG_TARGET_T1024RDB
696#define CONFIG_QE
697#define CONFIG_U_QE
698#endif
699
700#if defined(CONFIG_SPIFLASH)
701
702
703
704
705#define CONFIG_SYS_QE_FW_IN_SPIFLASH
706#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
707#define CONFIG_SYS_QE_FW_ADDR 0x130000
708#elif defined(CONFIG_SDCARD)
709
710
711
712
713
714#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
715#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
716#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
717#elif defined(CONFIG_NAND)
718#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
719#if defined(CONFIG_TARGET_T1024RDB)
720#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
721#define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
722#elif defined(CONFIG_TARGET_T1023RDB)
723#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
724#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
725#endif
726#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
727
728
729
730
731
732
733
734#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
735#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
736#else
737#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
738#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
739#define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
740#endif
741#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
742#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
743#endif
744
745#ifdef CONFIG_SYS_DPAA_FMAN
746#define CONFIG_FMAN_ENET
747#define CONFIG_PHYLIB_10G
748#define CONFIG_PHY_REALTEK
749#define CONFIG_PHY_AQUANTIA
750#if defined(CONFIG_TARGET_T1024RDB)
751#define RGMII_PHY1_ADDR 0x2
752#define RGMII_PHY2_ADDR 0x6
753#define SGMII_AQR_PHY_ADDR 0x2
754#define FM1_10GEC1_PHY_ADDR 0x1
755#elif defined(CONFIG_TARGET_T1023RDB)
756#define RGMII_PHY1_ADDR 0x1
757#define SGMII_RTK_PHY_ADDR 0x3
758#define SGMII_AQR_PHY_ADDR 0x2
759#endif
760#endif
761
762#ifdef CONFIG_FMAN_ENET
763#define CONFIG_MII
764#define CONFIG_ETHPRIME "FM1@DTSEC4"
765#define CONFIG_PHY_GIGE
766#endif
767
768
769
770
771#ifdef CONFIG_MTD_NOR_FLASH
772#define CONFIG_MTD_DEVICE
773#define CONFIG_MTD_PARTITIONS
774#define CONFIG_CMD_MTDPARTS
775#define CONFIG_FLASH_CFI_MTD
776#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
777 "spi0=spife110000.1"
778#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
779 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
780 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \
781 "1m(uboot),5m(kernel),128k(dtb),-(user)"
782#endif
783
784
785
786
787#define CONFIG_LOADS_ECHO
788#define CONFIG_SYS_LOADS_BAUD_CHANGE
789
790
791
792
793#define CONFIG_CMD_EEPROM
794#define CONFIG_CMD_ERRATA
795#define CONFIG_CMD_IRQ
796#define CONFIG_CMD_REGINFO
797
798#ifdef CONFIG_PCI
799#define CONFIG_CMD_PCI
800#endif
801
802
803
804
805#define CONFIG_SYS_LONGHELP
806#define CONFIG_CMDLINE_EDITING
807#define CONFIG_AUTO_COMPLETE
808#define CONFIG_SYS_LOAD_ADDR 0x2000000
809#ifdef CONFIG_CMD_KGDB
810#define CONFIG_SYS_CBSIZE 1024
811#else
812#define CONFIG_SYS_CBSIZE 256
813#endif
814#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
815#define CONFIG_SYS_MAXARGS 16
816#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
817
818
819
820
821
822
823#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
824#define CONFIG_SYS_BOOTM_LEN (64 << 20)
825
826#ifdef CONFIG_CMD_KGDB
827#define CONFIG_KGDB_BAUDRATE 230400
828#endif
829
830
831
832
833#define CONFIG_ROOTPATH "/opt/nfsroot"
834#define CONFIG_BOOTFILE "uImage"
835#define CONFIG_UBOOTPATH u-boot.bin
836#define CONFIG_LOADADDR 1000000
837#define __USB_PHY_TYPE utmi
838
839#ifdef CONFIG_ARCH_T1024
840#define CONFIG_BOARDNAME t1024rdb
841#define BANK_INTLV cs0_cs1
842#else
843#define CONFIG_BOARDNAME t1023rdb
844#define BANK_INTLV null
845#endif
846
847#define CONFIG_EXTRA_ENV_SETTINGS \
848 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
849 "bank_intlv=" __stringify(BANK_INTLV) "\0" \
850 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
851 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
852 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \
853 __stringify(CONFIG_BOARDNAME) ".dtb\0" \
854 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
855 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
856 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
857 "netdev=eth0\0" \
858 "tftpflash=tftpboot $loadaddr $uboot && " \
859 "protect off $ubootaddr +$filesize && " \
860 "erase $ubootaddr +$filesize && " \
861 "cp.b $loadaddr $ubootaddr $filesize && " \
862 "protect on $ubootaddr +$filesize && " \
863 "cmp.b $loadaddr $ubootaddr $filesize\0" \
864 "consoledev=ttyS0\0" \
865 "ramdiskaddr=2000000\0" \
866 "fdtaddr=1e00000\0" \
867 "bdev=sda3\0"
868
869#define CONFIG_LINUX \
870 "setenv bootargs root=/dev/ram rw " \
871 "console=$consoledev,$baudrate $othbootargs;" \
872 "setenv ramdiskaddr 0x02000000;" \
873 "setenv fdtaddr 0x00c00000;" \
874 "setenv loadaddr 0x1000000;" \
875 "bootm $loadaddr $ramdiskaddr $fdtaddr"
876
877#define CONFIG_NFSBOOTCOMMAND \
878 "setenv bootargs root=/dev/nfs rw " \
879 "nfsroot=$serverip:$rootpath " \
880 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
881 "console=$consoledev,$baudrate $othbootargs;" \
882 "tftp $loadaddr $bootfile;" \
883 "tftp $fdtaddr $fdtfile;" \
884 "bootm $loadaddr - $fdtaddr"
885
886#define CONFIG_BOOTCOMMAND CONFIG_LINUX
887
888
889#ifdef CONFIG_FSL_CAAM
890#define CONFIG_CMD_HASH
891#define CONFIG_SHA_HW_ACCEL
892#endif
893
894#include <asm/fsl_secure_boot.h>
895
896#endif
897
