1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23#ifndef __CONFIG_H
24#define __CONFIG_H
25
26
27
28
29
30#ifdef CONFIG_RAMBOOT_PBL
31#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
32#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
33#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg
34#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg
35#endif
36
37
38#define CONFIG_SYS_BOOK3E_HV
39#define CONFIG_MP
40
41
42#define CONFIG_DEEP_SLEEP
43
44#ifndef CONFIG_SYS_TEXT_BASE
45#define CONFIG_SYS_TEXT_BASE 0xeff40000
46#endif
47
48#ifndef CONFIG_RESET_VECTOR_ADDRESS
49#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
50#endif
51
52#define CONFIG_SYS_FSL_CPC
53#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
54#define CONFIG_PCI_INDIRECT_BRIDGE
55#define CONFIG_PCIE1
56#define CONFIG_PCIE2
57#define CONFIG_PCIE3
58#define CONFIG_PCIE4
59
60#define CONFIG_FSL_PCI_INIT
61#define CONFIG_SYS_PCI_64BIT
62
63#define CONFIG_ENV_OVERWRITE
64
65#ifndef CONFIG_MTD_NOR_FLASH
66#define CONFIG_ENV_IS_NOWHERE
67#else
68#define CONFIG_FLASH_CFI_DRIVER
69#define CONFIG_SYS_FLASH_CFI
70#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
71#endif
72
73#ifdef CONFIG_MTD_NOR_FLASH
74#if defined(CONFIG_SPIFLASH)
75#define CONFIG_SYS_EXTRA_ENV_RELOC
76#define CONFIG_ENV_IS_IN_SPI_FLASH
77#define CONFIG_ENV_SPI_BUS 0
78#define CONFIG_ENV_SPI_CS 0
79#define CONFIG_ENV_SPI_MAX_HZ 10000000
80#define CONFIG_ENV_SPI_MODE 0
81#define CONFIG_ENV_SIZE 0x2000
82#define CONFIG_ENV_OFFSET 0x100000
83#define CONFIG_ENV_SECT_SIZE 0x10000
84#elif defined(CONFIG_SDCARD)
85#define CONFIG_SYS_EXTRA_ENV_RELOC
86#define CONFIG_ENV_IS_IN_MMC
87#define CONFIG_SYS_MMC_ENV_DEV 0
88#define CONFIG_ENV_SIZE 0x2000
89#define CONFIG_ENV_OFFSET (512 * 1658)
90#elif defined(CONFIG_NAND)
91#define CONFIG_SYS_EXTRA_ENV_RELOC
92#define CONFIG_ENV_IS_IN_NAND
93#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
94#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
95#else
96#define CONFIG_ENV_IS_IN_FLASH
97#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
98#define CONFIG_ENV_SIZE 0x2000
99#define CONFIG_ENV_SECT_SIZE 0x20000
100#endif
101#else
102#define CONFIG_ENV_SIZE 0x2000
103#define CONFIG_ENV_SECT_SIZE 0x20000
104#endif
105
106#ifndef __ASSEMBLY__
107unsigned long get_board_sys_clk(void);
108unsigned long get_board_ddr_clk(void);
109#endif
110
111#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
112#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
113
114
115
116
117#define CONFIG_SYS_CACHE_STASHING
118#define CONFIG_BACKSIDE_L2_CACHE
119#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
120#define CONFIG_BTB
121#define CONFIG_DDR_ECC
122#ifdef CONFIG_DDR_ECC
123#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
124#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
125#endif
126
127#define CONFIG_ENABLE_36BIT_PHYS
128
129#define CONFIG_ADDR_MAP
130#define CONFIG_SYS_NUM_ADDR_MAP 64
131
132#define CONFIG_SYS_MEMTEST_START 0x00200000
133#define CONFIG_SYS_MEMTEST_END 0x00400000
134#define CONFIG_SYS_ALT_MEMTEST
135#define CONFIG_PANIC_HANG
136
137
138
139
140#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
141
142#define CONFIG_SYS_DCSRBAR 0xf0000000
143#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
144
145
146#define CONFIG_ID_EEPROM
147#define CONFIG_SYS_I2C_EEPROM_NXID
148#define CONFIG_SYS_EEPROM_BUS_NUM 0
149#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
150#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
151#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
152#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
153
154
155
156
157#define CONFIG_VERY_BIG_RAM
158#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
159#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
160
161#define CONFIG_DIMM_SLOTS_PER_CTLR 1
162#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
163
164#define CONFIG_DDR_SPD
165#define CONFIG_FSL_DDR_INTERACTIVE
166
167#define CONFIG_SYS_SPD_BUS_NUM 0
168#define SPD_EEPROM_ADDRESS 0x51
169
170#define CONFIG_SYS_SDRAM_SIZE 4096
171
172
173
174
175#define CONFIG_SYS_FLASH_BASE 0xe0000000
176#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
177
178#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
179#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
180 + 0x8000000) | \
181 CSPR_PORT_SIZE_16 | \
182 CSPR_MSEL_NOR | \
183 CSPR_V)
184#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
185#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
186 CSPR_PORT_SIZE_16 | \
187 CSPR_MSEL_NOR | \
188 CSPR_V)
189#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
190
191
192
193
194#define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
195
196
197#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
198#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
199 FTIM0_NOR_TEADC(0x5) | \
200 FTIM0_NOR_TEAHC(0x5))
201#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
202 FTIM1_NOR_TRAD_NOR(0x1A) |\
203 FTIM1_NOR_TSEQRAD_NOR(0x13))
204#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
205 FTIM2_NOR_TCH(0x4) | \
206 FTIM2_NOR_TWPH(0x0E) | \
207 FTIM2_NOR_TWP(0x1c))
208#define CONFIG_SYS_NOR_FTIM3 0x0
209
210#define CONFIG_SYS_FLASH_QUIET_TEST
211#define CONFIG_FLASH_SHOW_PROGRESS 45
212
213#define CONFIG_SYS_MAX_FLASH_BANKS 2
214#define CONFIG_SYS_MAX_FLASH_SECT 1024
215#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
216#define CONFIG_SYS_FLASH_WRITE_TOUT 500
217
218#define CONFIG_SYS_FLASH_EMPTY_INFO
219#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
220 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
221#define CONFIG_FSL_QIXIS
222#define QIXIS_BASE 0xffdf0000
223#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
224#define QIXIS_LBMAP_SWITCH 0x06
225#define QIXIS_LBMAP_MASK 0x0f
226#define QIXIS_LBMAP_SHIFT 0
227#define QIXIS_LBMAP_DFLTBANK 0x00
228#define QIXIS_LBMAP_ALTBANK 0x04
229#define QIXIS_RST_CTL_RESET 0x31
230#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
231#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
232#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
233#define QIXIS_RST_FORCE_MEM 0x01
234
235#define CONFIG_SYS_CSPR3_EXT (0xf)
236#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
237 | CSPR_PORT_SIZE_8 \
238 | CSPR_MSEL_GPCM \
239 | CSPR_V)
240#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
241#define CONFIG_SYS_CSOR3 0x0
242
243#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
244 FTIM0_GPCM_TEADC(0x0e) | \
245 FTIM0_GPCM_TEAHC(0x0e))
246#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
247 FTIM1_GPCM_TRAD(0x3f))
248#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
249 FTIM2_GPCM_TCH(0x8) | \
250 FTIM2_GPCM_TWP(0x1f))
251#define CONFIG_SYS_CS3_FTIM3 0x0
252
253#define CONFIG_NAND_FSL_IFC
254#define CONFIG_SYS_NAND_BASE 0xff800000
255#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
256
257#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
258#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
259 | CSPR_PORT_SIZE_8 \
260 | CSPR_MSEL_NAND \
261 | CSPR_V)
262#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
263
264#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
265 | CSOR_NAND_ECC_DEC_EN \
266 | CSOR_NAND_ECC_MODE_4 \
267 | CSOR_NAND_RAL_3 \
268 | CSOR_NAND_PGS_2K \
269 | CSOR_NAND_SPRZ_64 \
270 | CSOR_NAND_PB(64))
271
272#define CONFIG_SYS_NAND_ONFI_DETECTION
273
274
275#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
276 FTIM0_NAND_TWP(0x18) | \
277 FTIM0_NAND_TWCHT(0x07) | \
278 FTIM0_NAND_TWH(0x0a))
279#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
280 FTIM1_NAND_TWBE(0x39) | \
281 FTIM1_NAND_TRR(0x0e) | \
282 FTIM1_NAND_TRP(0x18))
283#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
284 FTIM2_NAND_TREH(0x0a) | \
285 FTIM2_NAND_TWHRE(0x1e))
286#define CONFIG_SYS_NAND_FTIM3 0x0
287
288#define CONFIG_SYS_NAND_DDR_LAW 11
289#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
290#define CONFIG_SYS_MAX_NAND_DEVICE 1
291#define CONFIG_CMD_NAND
292
293#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
294
295#if defined(CONFIG_NAND)
296#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
297#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
298#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
299#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
300#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
301#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
302#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
303#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
304#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
305#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
306#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
307#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
308#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
309#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
310#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
311#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
312#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
313#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
314#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
315#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
316#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
317#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
318#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
319#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
320#else
321#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
322#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
323#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
324#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
325#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
326#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
327#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
328#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
329#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
330#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
331#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
332#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
333#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
334#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
335#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
336#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
337#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
338#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
339#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
340#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
341#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
342#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
343#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
344#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
345#endif
346
347#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
348
349#if defined(CONFIG_RAMBOOT_PBL)
350#define CONFIG_SYS_RAMBOOT
351#endif
352
353#define CONFIG_BOARD_EARLY_INIT_R
354#define CONFIG_MISC_INIT_R
355
356#define CONFIG_HWCONFIG
357
358
359#define CONFIG_L1_INIT_RAM
360#define CONFIG_SYS_INIT_RAM_LOCK
361#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000
362#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
363#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
364
365#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
366 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
367 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
368#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
369
370#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
371 GENERATED_GBL_DATA_SIZE)
372#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
373
374#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
375#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
376
377
378
379
380
381#define CONFIG_CONS_INDEX 1
382#define CONFIG_SYS_NS16550_SERIAL
383#define CONFIG_SYS_NS16550_REG_SIZE 1
384#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
385
386#define CONFIG_SYS_BAUDRATE_TABLE \
387 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
388
389#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
390#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
391#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
392#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
393
394
395#define CONFIG_FSL_DIU_FB
396#ifdef CONFIG_FSL_DIU_FB
397#define CONFIG_FSL_DIU_CH7301
398#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
399#define CONFIG_VIDEO_LOGO
400#define CONFIG_VIDEO_BMP_LOGO
401#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
402
403
404
405
406#undef CONFIG_SYS_FLASH_EMPTY_INFO
407#endif
408
409
410#define CONFIG_SYS_I2C
411#define CONFIG_SYS_I2C_FSL
412#define CONFIG_SYS_FSL_I2C_SPEED 50000
413#define CONFIG_SYS_FSL_I2C2_SPEED 50000
414#define CONFIG_SYS_FSL_I2C3_SPEED 50000
415#define CONFIG_SYS_FSL_I2C4_SPEED 50000
416#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
417#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
418#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
419#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
420#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
421#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
422#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
423#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
424
425#define I2C_MUX_PCA_ADDR 0x77
426#define I2C_MUX_PCA_ADDR_PRI 0x77
427
428
429#define I2C_MUX_CH_DEFAULT 0x8
430#define I2C_MUX_CH_DIU 0xC
431
432
433#define CONFIG_SYS_I2C_LDI_ADDR 0x38
434#define CONFIG_SYS_I2C_DVI_ADDR 0x75
435
436
437
438
439#define RTC
440#define CONFIG_RTC_DS3231 1
441#define CONFIG_SYS_I2C_RTC_ADDR 0x68
442
443
444
445
446#define CONFIG_SF_DEFAULT_SPEED 10000000
447#define CONFIG_SF_DEFAULT_MODE 0
448
449
450
451
452
453
454#ifdef CONFIG_PCI
455
456#ifdef CONFIG_PCIE1
457#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
458#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
459#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
460#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
461#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
462#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
463#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
464#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
465#endif
466
467
468#ifdef CONFIG_PCIE2
469#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
470#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
471#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
472#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
473#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
474#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
475#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
476#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
477#endif
478
479
480#ifdef CONFIG_PCIE3
481#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
482#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
483#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
484#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000
485#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
486#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
487#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
488#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
489#endif
490
491
492#ifdef CONFIG_PCIE4
493#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
494#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
495#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
496#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000
497#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
498#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
499#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
500#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000
501#endif
502
503#define CONFIG_PCI_SCAN_SHOW
504#endif
505
506
507#define CONFIG_FSL_SATA_V2
508#ifdef CONFIG_FSL_SATA_V2
509#define CONFIG_LIBATA
510#define CONFIG_FSL_SATA
511
512#define CONFIG_SYS_SATA_MAX_DEVICE 2
513#define CONFIG_SATA1
514#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
515#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
516#define CONFIG_SATA2
517#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
518#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
519
520#define CONFIG_LBA48
521#define CONFIG_CMD_SATA
522#endif
523
524
525
526
527#define CONFIG_HAS_FSL_DR_USB
528
529#ifdef CONFIG_HAS_FSL_DR_USB
530#define CONFIG_USB_EHCI
531
532#ifdef CONFIG_USB_EHCI
533#define CONFIG_USB_EHCI_FSL
534#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
535#endif
536#endif
537
538#ifdef CONFIG_MMC
539#define CONFIG_FSL_ESDHC
540#define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
541#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
542#define CONFIG_FSL_ESDHC_ADAPTER_IDENT
543#endif
544
545
546#ifndef CONFIG_NOBQFMAN
547#define CONFIG_SYS_DPAA_QBMAN
548#define CONFIG_SYS_BMAN_NUM_PORTALS 10
549#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
550#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
551#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
552#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
553#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
554#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
555#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
556#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
557 CONFIG_SYS_BMAN_CENA_SIZE)
558#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
559#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
560#define CONFIG_SYS_QMAN_NUM_PORTALS 10
561#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
562#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
563#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
564#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
565#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
566#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
567#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
568#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
569 CONFIG_SYS_QMAN_CENA_SIZE)
570#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
571#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
572
573#define CONFIG_SYS_DPAA_FMAN
574#define CONFIG_SYS_DPAA_PME
575
576#define CONFIG_QE
577#define CONFIG_U_QE
578
579#if defined(CONFIG_SPIFLASH)
580
581
582
583
584#define CONFIG_SYS_QE_FW_IN_SPIFLASH
585#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
586#elif defined(CONFIG_SDCARD)
587
588
589
590
591
592#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
593#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
594#elif defined(CONFIG_NAND)
595#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
596#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
597#else
598#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
599#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
600#define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
601#endif
602#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
603#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
604#endif
605
606#ifdef CONFIG_SYS_DPAA_FMAN
607#define CONFIG_FMAN_ENET
608#define CONFIG_PHYLIB_10G
609#define CONFIG_PHY_VITESSE
610#define CONFIG_PHY_REALTEK
611#define CONFIG_PHY_TERANETICS
612#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
613#define SGMII_CARD_PORT2_PHY_ADDR 0x10
614#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
615#define SGMII_CARD_PORT4_PHY_ADDR 0x11
616#endif
617
618#ifdef CONFIG_FMAN_ENET
619#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01
620#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02
621
622#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
623#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
624#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
625#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
626
627#define CONFIG_MII
628#define CONFIG_ETHPRIME "FM1@DTSEC1"
629#define CONFIG_PHY_GIGE
630#endif
631
632
633#define CONFIG_VSC9953
634#define CONFIG_CMD_ETHSW
635#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14
636#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18
637
638
639
640
641#ifdef CONFIG_MTD_NOR_FLASH
642#define CONFIG_MTD_DEVICE
643#define CONFIG_MTD_PARTITIONS
644#define CONFIG_CMD_MTDPARTS
645#define CONFIG_FLASH_CFI_MTD
646#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
647 "spi0=spife110000.0"
648#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
649 "128k(dtb),96m(fs),-(user);"\
650 "fff800000.flash:2m(uboot),9m(kernel),"\
651 "128k(dtb),96m(fs),-(user);spife110000.0:" \
652 "2m(uboot),9m(kernel),128k(dtb),-(user)"
653#endif
654
655
656
657
658#define CONFIG_LOADS_ECHO
659#define CONFIG_SYS_LOADS_BAUD_CHANGE
660
661
662
663
664#define CONFIG_CMD_EEPROM
665#define CONFIG_CMD_ERRATA
666#define CONFIG_CMD_IRQ
667#define CONFIG_CMD_REGINFO
668
669#ifdef CONFIG_PCI
670#define CONFIG_CMD_PCI
671#endif
672
673
674#ifdef CONFIG_FSL_CAAM
675#define CONFIG_CMD_HASH
676#define CONFIG_SHA_HW_ACCEL
677#endif
678
679
680
681
682#define CONFIG_SYS_LONGHELP
683#define CONFIG_CMDLINE_EDITING
684#define CONFIG_AUTO_COMPLETE
685#define CONFIG_SYS_LOAD_ADDR 0x2000000
686#ifdef CONFIG_CMD_KGDB
687#define CONFIG_SYS_CBSIZE 1024
688#else
689#define CONFIG_SYS_CBSIZE 256
690#endif
691#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
692#define CONFIG_SYS_MAXARGS 16
693#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
694
695
696
697
698
699
700#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
701#define CONFIG_SYS_BOOTM_LEN (64 << 20)
702
703#ifdef CONFIG_CMD_KGDB
704#define CONFIG_KGDB_BAUDRATE 230400
705#endif
706
707
708
709
710#define CONFIG_ROOTPATH "/opt/nfsroot"
711#define CONFIG_BOOTFILE "uImage"
712#define CONFIG_UBOOTPATH "u-boot.bin"
713
714
715#define CONFIG_LOADADDR 1000000
716
717#define __USB_PHY_TYPE utmi
718
719#define CONFIG_EXTRA_ENV_SETTINGS \
720 "hwconfig=fsl_ddr:bank_intlv=auto;" \
721 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
722 "netdev=eth0\0" \
723 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
724 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
725 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
726 "tftpflash=tftpboot $loadaddr $uboot && " \
727 "protect off $ubootaddr +$filesize && " \
728 "erase $ubootaddr +$filesize && " \
729 "cp.b $loadaddr $ubootaddr $filesize && " \
730 "protect on $ubootaddr +$filesize && " \
731 "cmp.b $loadaddr $ubootaddr $filesize\0" \
732 "consoledev=ttyS0\0" \
733 "ramdiskaddr=2000000\0" \
734 "ramdiskfile=t1040qds/ramdisk.uboot\0" \
735 "fdtaddr=1e00000\0" \
736 "fdtfile=t1040qds/t1040qds.dtb\0" \
737 "bdev=sda3\0"
738
739#define CONFIG_LINUX \
740 "setenv bootargs root=/dev/ram rw " \
741 "console=$consoledev,$baudrate $othbootargs;" \
742 "setenv ramdiskaddr 0x02000000;" \
743 "setenv fdtaddr 0x00c00000;" \
744 "setenv loadaddr 0x1000000;" \
745 "bootm $loadaddr $ramdiskaddr $fdtaddr"
746
747#define CONFIG_HDBOOT \
748 "setenv bootargs root=/dev/$bdev rw " \
749 "console=$consoledev,$baudrate $othbootargs;" \
750 "tftp $loadaddr $bootfile;" \
751 "tftp $fdtaddr $fdtfile;" \
752 "bootm $loadaddr - $fdtaddr"
753
754#define CONFIG_NFSBOOTCOMMAND \
755 "setenv bootargs root=/dev/nfs rw " \
756 "nfsroot=$serverip:$rootpath " \
757 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
758 "console=$consoledev,$baudrate $othbootargs;" \
759 "tftp $loadaddr $bootfile;" \
760 "tftp $fdtaddr $fdtfile;" \
761 "bootm $loadaddr - $fdtaddr"
762
763#define CONFIG_RAMBOOTCOMMAND \
764 "setenv bootargs root=/dev/ram rw " \
765 "console=$consoledev,$baudrate $othbootargs;" \
766 "tftp $ramdiskaddr $ramdiskfile;" \
767 "tftp $loadaddr $bootfile;" \
768 "tftp $fdtaddr $fdtfile;" \
769 "bootm $loadaddr $ramdiskaddr $fdtaddr"
770
771#define CONFIG_BOOTCOMMAND CONFIG_LINUX
772
773#include <asm/fsl_secure_boot.h>
774
775#endif
776