LXR uboot/include/configs/T4240QDS.h

   1/*
   2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7/*
   8 * T4240 QDS board configuration file
   9 */
  10#ifndef __CONFIG_H
  11#define __CONFIG_H
  12
  13#define CONFIG_FSL_SATA_V2
  14#define CONFIG_PCIE4
  15
  16#define CONFIG_ICS307_REFCLK_HZ         25000000  /* ICS307 ref clk freq */
  17
  18#ifdef CONFIG_RAMBOOT_PBL
  19#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg
  20#if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD)
  21#define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  22#define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  23#else
  24#define CONFIG_SPL_FLUSH_IMAGE
  25#define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  26#define CONFIG_SYS_TEXT_BASE            0x00201000
  27#define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  28#define CONFIG_SPL_PAD_TO               0x40000
  29#define CONFIG_SPL_MAX_SIZE             0x28000
  30#define RESET_VECTOR_OFFSET             0x27FFC
  31#define BOOT_PAGE_OFFSET                0x27000
  32
  33#ifdef  CONFIG_NAND
  34#define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  35#define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  36#define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  37#define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  38#define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  39#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_nand_rcw.cfg
  40#define CONFIG_SPL_NAND_BOOT
  41#endif
  42
  43#ifdef  CONFIG_SDCARD
  44#define CONFIG_RESET_VECTOR_ADDRESS     0x200FFC
  45#define CONFIG_SPL_MMC_MINIMAL
  46#define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  47#define CONFIG_SYS_MMC_U_BOOT_DST       0x00200000
  48#define CONFIG_SYS_MMC_U_BOOT_START     0x00200000
  49#define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  50#ifndef CONFIG_SPL_BUILD
  51#define CONFIG_SYS_MPC85XX_NO_RESETVEC
  52#endif
  53#define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  54#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_sd_rcw.cfg
  55#define CONFIG_SPL_MMC_BOOT
  56#endif
  57
  58#ifdef CONFIG_SPL_BUILD
  59#define CONFIG_SPL_SKIP_RELOCATE
  60#define CONFIG_SPL_COMMON_INIT_DDR
  61#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  62#endif
  63
  64#endif
  65#endif /* CONFIG_RAMBOOT_PBL */
  66
  67#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  68/* Set 1M boot space */
  69#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  70#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  71                (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  72#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  73#endif
  74
  75#define CONFIG_SRIO_PCIE_BOOT_MASTER
  76#define CONFIG_DDR_ECC
  77
  78#include "t4qds.h"
  79
  80#ifndef CONFIG_MTD_NOR_FLASH
  81#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
  82#define CONFIG_ENV_IS_NOWHERE
  83#endif
  84#else
  85#define CONFIG_FLASH_CFI_DRIVER
  86#define CONFIG_SYS_FLASH_CFI
  87#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  88#endif
  89
  90#if defined(CONFIG_SPIFLASH)
  91#define CONFIG_SYS_EXTRA_ENV_RELOC
  92#define CONFIG_ENV_IS_IN_SPI_FLASH
  93#define CONFIG_ENV_SPI_BUS              0
  94#define CONFIG_ENV_SPI_CS               0
  95#define CONFIG_ENV_SPI_MAX_HZ           10000000
  96#define CONFIG_ENV_SPI_MODE             0
  97#define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
  98#define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
  99#define CONFIG_ENV_SECT_SIZE            0x10000
 100#elif defined(CONFIG_SDCARD)
 101#define CONFIG_SYS_EXTRA_ENV_RELOC
 102#define CONFIG_ENV_IS_IN_MMC
 103#define CONFIG_SYS_MMC_ENV_DEV          0
 104#define CONFIG_ENV_SIZE                 0x2000
 105#define CONFIG_ENV_OFFSET               (512 * 0x800)
 106#elif defined(CONFIG_NAND)
 107#define CONFIG_SYS_EXTRA_ENV_RELOC
 108#define CONFIG_ENV_IS_IN_NAND
 109#define CONFIG_ENV_SIZE                 0x2000
 110#define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 111#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 112#define CONFIG_ENV_IS_IN_REMOTE
 113#define CONFIG_ENV_ADDR         0xffe20000
 114#define CONFIG_ENV_SIZE         0x2000
 115#elif defined(CONFIG_ENV_IS_NOWHERE)
 116#define CONFIG_ENV_SIZE         0x2000
 117#else
 118#define CONFIG_ENV_IS_IN_FLASH
 119#define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 120#define CONFIG_ENV_SIZE         0x2000
 121#define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 122#endif
 123
 124#define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
 125#define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 126
 127#ifndef __ASSEMBLY__
 128unsigned long get_board_sys_clk(void);
 129unsigned long get_board_ddr_clk(void);
 130#endif
 131
 132/* EEPROM */
 133#define CONFIG_ID_EEPROM
 134#define CONFIG_SYS_I2C_EEPROM_NXID
 135#define CONFIG_SYS_EEPROM_BUS_NUM       0
 136#define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 137#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 138
 139/*
 140 * DDR Setup
 141 */
 142#define CONFIG_SYS_SPD_BUS_NUM  0
 143#define SPD_EEPROM_ADDRESS1     0x51
 144#define SPD_EEPROM_ADDRESS2     0x52
 145#define SPD_EEPROM_ADDRESS3     0x53
 146#define SPD_EEPROM_ADDRESS4     0x54
 147#define SPD_EEPROM_ADDRESS5     0x55
 148#define SPD_EEPROM_ADDRESS6     0x56
 149#define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 150#define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 151
 152/*
 153 * IFC Definitions
 154 */
 155#define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 156#define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 157                                + 0x8000000) | \
 158                                CSPR_PORT_SIZE_16 | \
 159                                CSPR_MSEL_NOR | \
 160                                CSPR_V)
 161#define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 162#define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 163                                CSPR_PORT_SIZE_16 | \
 164                                CSPR_MSEL_NOR | \
 165                                CSPR_V)
 166#define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 167/* NOR Flash Timing Params */
 168#define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 169
 170#define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 171                                FTIM0_NOR_TEADC(0x5) | \
 172                                FTIM0_NOR_TEAHC(0x5))
 173#define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 174                                FTIM1_NOR_TRAD_NOR(0x1A) |\
 175                                FTIM1_NOR_TSEQRAD_NOR(0x13))
 176#define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 177                                FTIM2_NOR_TCH(0x4) | \
 178                                FTIM2_NOR_TWPH(0x0E) | \
 179                                FTIM2_NOR_TWP(0x1c))
 180#define CONFIG_SYS_NOR_FTIM3    0x0
 181
 182#define CONFIG_SYS_FLASH_QUIET_TEST
 183#define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 184
 185#define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 186#define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 187#define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 188#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 189
 190#define CONFIG_SYS_FLASH_EMPTY_INFO
 191#define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 192                                        + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 193
 194#define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 195#define QIXIS_BASE                      0xffdf0000
 196#define QIXIS_LBMAP_SWITCH              6
 197#define QIXIS_LBMAP_MASK                0x0f
 198#define QIXIS_LBMAP_SHIFT               0
 199#define QIXIS_LBMAP_DFLTBANK            0x00
 200#define QIXIS_LBMAP_ALTBANK             0x04
 201#define QIXIS_RST_CTL_RESET             0x83
 202#define QIXIS_RST_FORCE_MEM             0x1
 203#define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 204#define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 205#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 206#define QIXIS_BRDCFG5                   0x55
 207#define QIXIS_MUX_SDHC                  2
 208#define QIXIS_MUX_SDHC_WIDTH8           1
 209#define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 210
 211#define CONFIG_SYS_CSPR3_EXT    (0xf)
 212#define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 213                                | CSPR_PORT_SIZE_8 \
 214                                | CSPR_MSEL_GPCM \
 215                                | CSPR_V)
 216#define CONFIG_SYS_AMASK3       IFC_AMASK(4*1024)
 217#define CONFIG_SYS_CSOR3        0x0
 218/* QIXIS Timing parameters for IFC CS3 */
 219#define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 220                                        FTIM0_GPCM_TEADC(0x0e) | \
 221                                        FTIM0_GPCM_TEAHC(0x0e))
 222#define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 223                                        FTIM1_GPCM_TRAD(0x3f))
 224#define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 225                                        FTIM2_GPCM_TCH(0x8) | \
 226                                        FTIM2_GPCM_TWP(0x1f))
 227#define CONFIG_SYS_CS3_FTIM3            0x0
 228
 229/* NAND Flash on IFC */
 230#define CONFIG_NAND_FSL_IFC
 231#define CONFIG_SYS_NAND_BASE            0xff800000
 232#define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 233
 234#define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 235#define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 236                                | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 237                                | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 238                                | CSPR_V)
 239#define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 240
 241#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 242                                | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 243                                | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 244                                | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 245                                | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 246                                | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 247                                | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 248
 249#define CONFIG_SYS_NAND_ONFI_DETECTION
 250
 251/* ONFI NAND Flash mode0 Timing Params */
 252#define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 253                                        FTIM0_NAND_TWP(0x18)   | \
 254                                        FTIM0_NAND_TWCHT(0x07) | \
 255                                        FTIM0_NAND_TWH(0x0a))
 256#define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 257                                        FTIM1_NAND_TWBE(0x39)  | \
 258                                        FTIM1_NAND_TRR(0x0e)   | \
 259                                        FTIM1_NAND_TRP(0x18))
 260#define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 261                                        FTIM2_NAND_TREH(0x0a) | \
 262                                        FTIM2_NAND_TWHRE(0x1e))
 263#define CONFIG_SYS_NAND_FTIM3           0x0
 264
 265#define CONFIG_SYS_NAND_DDR_LAW         11
 266
 267#define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 268#define CONFIG_SYS_MAX_NAND_DEVICE      1
 269#define CONFIG_CMD_NAND
 270
 271#define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 272#define CONFIG_SYS_NAND_MAX_OOBFREE     2
 273#define CONFIG_SYS_NAND_MAX_ECCPOS      256
 274
 275#if defined(CONFIG_NAND)
 276#define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 277#define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 278#define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 279#define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 280#define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 281#define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 282#define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 283#define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 284#define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 285#define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 286#define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 287#define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 288#define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 289#define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 290#define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 291#define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 292#define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 293#define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 294#define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 295#define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 296#define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 297#define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 298#define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 299#define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 300#else
 301#define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 302#define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 303#define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 304#define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 305#define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 306#define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 307#define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 308#define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 309#define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 310#define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 311#define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 312#define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 313#define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 314#define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 315#define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 316#define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 317#define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 318#define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 319#define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 320#define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 321#define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 322#define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 323#define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 324#define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 325#endif
 326
 327#if defined(CONFIG_RAMBOOT_PBL)
 328#define CONFIG_SYS_RAMBOOT
 329#endif
 330
 331/* I2C */
 332#define CONFIG_SYS_FSL_I2C_SPEED        100000  /* I2C speed */
 333#define CONFIG_SYS_FSL_I2C2_SPEED       100000  /* I2C2 speed */
 334#define I2C_MUX_PCA_ADDR_PRI            0x77 /* I2C bus multiplexer,primary */
 335#define I2C_MUX_PCA_ADDR_SEC            0x76 /* I2C bus multiplexer,secondary */
 336
 337#define I2C_MUX_CH_DEFAULT      0x8
 338#define I2C_MUX_CH_VOL_MONITOR  0xa
 339#define I2C_MUX_CH_VSC3316_FS   0xc
 340#define I2C_MUX_CH_VSC3316_BS   0xd
 341
 342/* Voltage monitor on channel 2*/
 343#define I2C_VOL_MONITOR_ADDR            0x40
 344#define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
 345#define I2C_VOL_MONITOR_BUS_V_OVF       0x1
 346#define I2C_VOL_MONITOR_BUS_V_SHIFT     3
 347
 348/* VSC Crossbar switches */
 349#define CONFIG_VSC_CROSSBAR
 350#define VSC3316_FSM_TX_ADDR     0x70
 351#define VSC3316_FSM_RX_ADDR     0x71
 352
 353/*
 354 * RapidIO
 355 */
 356
 357/*
 358 * for slave u-boot IMAGE instored in master memory space,
 359 * PHYS must be aligned based on the SIZE
 360 */
 361#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 362#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 363#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 364#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 365/*
 366 * for slave UCODE and ENV instored in master memory space,
 367 * PHYS must be aligned based on the SIZE
 368 */
 369#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 370#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 371#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 372
 373/* slave core release by master*/
 374#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 375#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 376
 377/*
 378 * SRIO_PCIE_BOOT - SLAVE
 379 */
 380#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 381#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 382#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 383                (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 384#endif
 385/*
 386 * eSPI - Enhanced SPI
 387 */
 388#define CONFIG_SF_DEFAULT_SPEED         10000000
 389#define CONFIG_SF_DEFAULT_MODE          0
 390
 391/* Qman/Bman */
 392#ifndef CONFIG_NOBQFMAN
 393#define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 394#define CONFIG_SYS_BMAN_NUM_PORTALS     50
 395#define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 396#define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 397#define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 398#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 399#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 400#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 401#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 402#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 403                                        CONFIG_SYS_BMAN_CENA_SIZE)
 404#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 405#define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 406#define CONFIG_SYS_QMAN_NUM_PORTALS     50
 407#define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 408#define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 409#define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 410#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 411#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 412#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 413#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 414#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 415                                        CONFIG_SYS_QMAN_CENA_SIZE)
 416#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 417#define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 418
 419#define CONFIG_SYS_DPAA_FMAN
 420#define CONFIG_SYS_DPAA_PME
 421#define CONFIG_SYS_PMAN
 422#define CONFIG_SYS_DPAA_DCE
 423#define CONFIG_SYS_DPAA_RMAN
 424#define CONFIG_SYS_INTERLAKEN
 425
 426/* Default address of microcode for the Linux Fman driver */
 427#if defined(CONFIG_SPIFLASH)
 428/*
 429 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 430 * env, so we got 0x110000.
 431 */
 432#define CONFIG_SYS_QE_FW_IN_SPIFLASH
 433#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 434#elif defined(CONFIG_SDCARD)
 435/*
 436 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 437 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 438 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 439 */
 440#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 441#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 442#elif defined(CONFIG_NAND)
 443#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 444#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 445#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 446/*
 447 * Slave has no ucode locally, it can fetch this from remote. When implementing
 448 * in two corenet boards, slave's ucode could be stored in master's memory
 449 * space, the address can be mapped from slave TLB->slave LAW->
 450 * slave SRIO or PCIE outbound window->master inbound window->
 451 * master LAW->the ucode address in master's memory space.
 452 */
 453#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 454#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 455#else
 456#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 457#define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 458#endif
 459#define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 460#define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 461#endif /* CONFIG_NOBQFMAN */
 462
 463#ifdef CONFIG_SYS_DPAA_FMAN
 464#define CONFIG_FMAN_ENET
 465#define CONFIG_PHYLIB_10G
 466#define CONFIG_PHY_VITESSE
 467#define CONFIG_PHY_TERANETICS
 468#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 469#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 470#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 471#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 472#define FM1_10GEC1_PHY_ADDR     0x0
 473#define FM1_10GEC2_PHY_ADDR     0x1
 474#define FM2_10GEC1_PHY_ADDR     0x2
 475#define FM2_10GEC2_PHY_ADDR     0x3
 476#endif
 477
 478/* SATA */
 479#ifdef CONFIG_FSL_SATA_V2
 480#define CONFIG_LIBATA
 481#define CONFIG_FSL_SATA
 482
 483#define CONFIG_SYS_SATA_MAX_DEVICE      2
 484#define CONFIG_SATA1
 485#define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 486#define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 487#define CONFIG_SATA2
 488#define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 489#define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 490
 491#define CONFIG_LBA48
 492#define CONFIG_CMD_SATA
 493#endif
 494
 495#ifdef CONFIG_FMAN_ENET
 496#define CONFIG_MII              /* MII PHY management */
 497#define CONFIG_ETHPRIME         "FM1@DTSEC1"
 498#define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 499#endif
 500
 501/* Hash command with SHA acceleration supported in hardware */
 502#ifdef CONFIG_FSL_CAAM
 503#define CONFIG_CMD_HASH
 504#define CONFIG_SHA_HW_ACCEL
 505#endif
 506
 507/*
 508* USB
 509*/
 510#define CONFIG_USB_EHCI
 511#define CONFIG_USB_EHCI_FSL
 512#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 513#define CONFIG_HAS_FSL_DR_USB
 514
 515#ifdef CONFIG_MMC
 516#define CONFIG_FSL_ESDHC
 517#define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 518#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 519#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 520#define CONFIG_ESDHC_DETECT_QUIRK \
 521        (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \
 522        IS_SVR_REV(get_svr(), 1, 0))
 523#define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \
 524        (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8))
 525#endif
 526
 527
 528#define __USB_PHY_TYPE  utmi
 529
 530/*
 531 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
 532 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
 533 * interleaving. It can be cacheline, page, bank, superbank.
 534 * See doc/README.fsl-ddr for details.
 535 */
 536#ifdef CONFIG_ARCH_T4240
 537#define CTRL_INTLV_PREFERED 3way_4KB
 538#else
 539#define CTRL_INTLV_PREFERED cacheline
 540#endif
 541
 542#define CONFIG_EXTRA_ENV_SETTINGS                               \
 543        "hwconfig=fsl_ddr:"                                     \
 544        "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 545        "bank_intlv=auto;"                                      \
 546        "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 547        "netdev=eth0\0"                                         \
 548        "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 549        "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"             \
 550        "tftpflash=tftpboot $loadaddr $uboot && "               \
 551        "protect off $ubootaddr +$filesize && "                 \
 552        "erase $ubootaddr +$filesize && "                       \
 553        "cp.b $loadaddr $ubootaddr $filesize && "               \
 554        "protect on $ubootaddr +$filesize && "                  \
 555        "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 556        "consoledev=ttyS0\0"                                    \
 557        "ramdiskaddr=2000000\0"                                 \
 558        "ramdiskfile=t4240qds/ramdisk.uboot\0"                  \
 559        "fdtaddr=1e00000\0"                                     \
 560        "fdtfile=t4240qds/t4240qds.dtb\0"                               \
 561        "bdev=sda3\0"
 562
 563#define CONFIG_HVBOOT                           \
 564        "setenv bootargs config-addr=0x60000000; "      \
 565        "bootm 0x01000000 - 0x00f00000"
 566
 567#define CONFIG_ALU                              \
 568        "setenv bootargs root=/dev/$bdev rw "           \
 569        "console=$consoledev,$baudrate $othbootargs;"   \
 570        "cpu 1 release 0x01000000 - - -;"               \
 571        "cpu 2 release 0x01000000 - - -;"               \
 572        "cpu 3 release 0x01000000 - - -;"               \
 573        "cpu 4 release 0x01000000 - - -;"               \
 574        "cpu 5 release 0x01000000 - - -;"               \
 575        "cpu 6 release 0x01000000 - - -;"               \
 576        "cpu 7 release 0x01000000 - - -;"               \
 577        "go 0x01000000"
 578
 579#define CONFIG_LINUX                            \
 580        "setenv bootargs root=/dev/ram rw "             \
 581        "console=$consoledev,$baudrate $othbootargs;"   \
 582        "setenv ramdiskaddr 0x02000000;"                \
 583        "setenv fdtaddr 0x00c00000;"                    \
 584        "setenv loadaddr 0x1000000;"                    \
 585        "bootm $loadaddr $ramdiskaddr $fdtaddr"
 586
 587#define CONFIG_HDBOOT                                   \
 588        "setenv bootargs root=/dev/$bdev rw "           \
 589        "console=$consoledev,$baudrate $othbootargs;"   \
 590        "tftp $loadaddr $bootfile;"                     \
 591        "tftp $fdtaddr $fdtfile;"                       \
 592        "bootm $loadaddr - $fdtaddr"
 593
 594#define CONFIG_NFSBOOTCOMMAND                   \
 595        "setenv bootargs root=/dev/nfs rw "     \
 596        "nfsroot=$serverip:$rootpath "          \
 597        "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 598        "console=$consoledev,$baudrate $othbootargs;"   \
 599        "tftp $loadaddr $bootfile;"             \
 600        "tftp $fdtaddr $fdtfile;"               \
 601        "bootm $loadaddr - $fdtaddr"
 602
 603#define CONFIG_RAMBOOTCOMMAND                           \
 604        "setenv bootargs root=/dev/ram rw "             \
 605        "console=$consoledev,$baudrate $othbootargs;"   \
 606        "tftp $ramdiskaddr $ramdiskfile;"               \
 607        "tftp $loadaddr $bootfile;"                     \
 608        "tftp $fdtaddr $fdtfile;"                       \
 609        "bootm $loadaddr $ramdiskaddr $fdtaddr"
 610
 611#define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 612
 613#include <asm/fsl_secure_boot.h>
 614
 615#endif  /* __CONFIG_H */
 616