1/* 2 * (C) Copyright 2000-2014 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* 9 * board/config.h - configuration options, board specific 10 */ 11 12#ifndef __CONFIG_H 13#define __CONFIG_H 14 15/* 16 * High Level Configuration Options 17 * (easy to change) 18 */ 19 20#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ 21#define CONFIG_TQM850M 1 /* ...on a TQM8xxM module */ 22 23#define CONFIG_SYS_TEXT_BASE 0x40000000 24 25#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 26#define CONFIG_SYS_SMC_RXBUFLEN 128 27#define CONFIG_SYS_MAXIDLE 10 28 29#define CONFIG_BOOTCOUNT_LIMIT 30 31 32#define CONFIG_BOARD_TYPES 1 /* support board types */ 33 34#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" 35 36#undef CONFIG_BOOTARGS 37 38#define CONFIG_EXTRA_ENV_SETTINGS \ 39 "netdev=eth0\0" \ 40 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 41 "nfsroot=${serverip}:${rootpath}\0" \ 42 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 43 "addip=setenv bootargs ${bootargs} " \ 44 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 45 ":${hostname}:${netdev}:off panic=1\0" \ 46 "flash_nfs=run nfsargs addip;" \ 47 "bootm ${kernel_addr}\0" \ 48 "flash_self=run ramargs addip;" \ 49 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 50 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 51 "rootpath=/opt/eldk/ppc_8xx\0" \ 52 "hostname=TQM850M\0" \ 53 "bootfile=TQM850M/uImage\0" \ 54 "fdt_addr=40080000\0" \ 55 "kernel_addr=400A0000\0" \ 56 "ramdisk_addr=40280000\0" \ 57 "u-boot=TQM850M/u-image.bin\0" \ 58 "load=tftp 200000 ${u-boot}\0" \ 59 "update=prot off 40000000 +${filesize};" \ 60 "era 40000000 +${filesize};" \ 61 "cp.b 200000 40000000 ${filesize};" \ 62 "sete filesize;save\0" \ 63 "" 64#define CONFIG_BOOTCOMMAND "run flash_self" 65 66#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 67#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 68 69#undef CONFIG_WATCHDOG /* watchdog disabled */ 70 71#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 72 73/* 74 * BOOTP options 75 */ 76#define CONFIG_BOOTP_SUBNETMASK 77#define CONFIG_BOOTP_GATEWAY 78#define CONFIG_BOOTP_HOSTNAME 79#define CONFIG_BOOTP_BOOTPATH 80#define CONFIG_BOOTP_BOOTFILESIZE 81 82#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 83 84/* 85 * Command line configuration. 86 */ 87#define CONFIG_CMD_IDE 88#define CONFIG_CMD_JFFS2 89 90#define CONFIG_NETCONSOLE 91 92/* 93 * Miscellaneous configurable options 94 */ 95#define CONFIG_SYS_LONGHELP /* undef to save memory */ 96 97#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 98 99#if defined(CONFIG_CMD_KGDB) 100#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 101#else 102#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 103#endif 104#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 105#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 106#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 107 108#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 109#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 110 111#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 112 113/* 114 * Low Level Configuration Settings 115 * (address mappings, register initial values, etc.) 116 * You should know what you are doing if you make changes here. 117 */ 118/*----------------------------------------------------------------------- 119 * Internal Memory Mapped Register 120 */ 121#define CONFIG_SYS_IMMR 0xFFF00000 122 123/*----------------------------------------------------------------------- 124 * Definitions for initial stack pointer and data area (in DPRAM) 125 */ 126#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 127#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 128#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 129#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 130 131/*----------------------------------------------------------------------- 132 * Start addresses for the final memory configuration 133 * (Set up by the startup code) 134 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 135 */ 136#define CONFIG_SYS_SDRAM_BASE 0x00000000 137#define CONFIG_SYS_FLASH_BASE 0x40000000 138#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 139#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 140#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 141 142/* 143 * For booting Linux, the board info and command line data 144 * have to be in the first 8 MB of memory, since this is 145 * the maximum mapped by the Linux kernel during initialization. 146 */ 147#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 148 149/*----------------------------------------------------------------------- 150 * FLASH organization 151 */ 152 153/* use CFI flash driver */ 154#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 155#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 156#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 157#define CONFIG_SYS_FLASH_EMPTY_INFO 158#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 159#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 160#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 161 162#define CONFIG_ENV_IS_IN_FLASH 1 163#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ 164#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ 165#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ 166 167/* Address and size of Redundant Environment Sector */ 168#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) 169#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 170 171#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 172 173#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 174 175/*----------------------------------------------------------------------- 176 * Dynamic MTD partition support 177 */ 178#define CONFIG_CMD_MTDPARTS 179#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 180#define CONFIG_FLASH_CFI_MTD 181#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" 182 183#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ 184 "128k(dtb)," \ 185 "1920k(kernel)," \ 186 "5632(rootfs)," \ 187 "4m(data)" 188 189/*----------------------------------------------------------------------- 190 * Hardware Information Block 191 */ 192#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 193#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 194#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 195 196/*----------------------------------------------------------------------- 197 * Cache Configuration 198 */ 199#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 200#if defined(CONFIG_CMD_KGDB) 201#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 202#endif 203 204/*----------------------------------------------------------------------- 205 * SYPCR - System Protection Control 11-9 206 * SYPCR can only be written once after reset! 207 *----------------------------------------------------------------------- 208 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 209 */ 210#if defined(CONFIG_WATCHDOG) 211#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 212 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 213#else 214#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 215#endif 216 217/*----------------------------------------------------------------------- 218 * SIUMCR - SIU Module Configuration 11-6 219 *----------------------------------------------------------------------- 220 * PCMCIA config., multi-function pin tri-state 221 */ 222#ifndef CONFIG_CAN_DRIVER 223#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 224#else /* we must activate GPL5 in the SIUMCR for CAN */ 225#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 226#endif /* CONFIG_CAN_DRIVER */ 227 228/*----------------------------------------------------------------------- 229 * TBSCR - Time Base Status and Control 11-26 230 *----------------------------------------------------------------------- 231 * Clear Reference Interrupt Status, Timebase freezing enabled 232 */ 233#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 234 235/*----------------------------------------------------------------------- 236 * RTCSC - Real-Time Clock Status and Control Register 11-27 237 *----------------------------------------------------------------------- 238 */ 239#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 240 241/*----------------------------------------------------------------------- 242 * PISCR - Periodic Interrupt Status and Control 11-31 243 *----------------------------------------------------------------------- 244 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 245 */ 246#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 247 248/*----------------------------------------------------------------------- 249 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 250 *----------------------------------------------------------------------- 251 * Reset PLL lock status sticky bit, timer expired status bit and timer 252 * interrupt status bit 253 */ 254#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 255 256/*----------------------------------------------------------------------- 257 * SCCR - System Clock and reset Control Register 15-27 258 *----------------------------------------------------------------------- 259 * Set clock output, timebase and RTC source and divider, 260 * power management and some other internal clocks 261 */ 262#define SCCR_MASK SCCR_EBDF11 263#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 264 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 265 SCCR_DFALCD00) 266 267/*----------------------------------------------------------------------- 268 * PCMCIA stuff 269 *----------------------------------------------------------------------- 270 * 271 */ 272#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 273#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 274#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 275#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 276#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 277#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 278#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 279#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 280 281/*----------------------------------------------------------------------- 282 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 283 *----------------------------------------------------------------------- 284 */ 285 286#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ 287#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 288 289#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 290#undef CONFIG_IDE_LED /* LED for ide not supported */ 291#undef CONFIG_IDE_RESET /* reset for ide not supported */ 292 293#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 294#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 295 296#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 297 298#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 299 300/* Offset for data I/O */ 301#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 302 303/* Offset for normal register accesses */ 304#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 305 306/* Offset for alternate registers */ 307#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 308 309/*----------------------------------------------------------------------- 310 * 311 *----------------------------------------------------------------------- 312 * 313 */ 314#define CONFIG_SYS_DER 0 315 316/* 317 * Init Memory Controller: 318 * 319 * BR0/1 and OR0/1 (FLASH) 320 */ 321 322#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 323#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 324 325/* used to re-map FLASH both when starting from SRAM or FLASH: 326 * restrict access enough to keep SRAM working (if any) 327 * but not too much to meddle with FLASH accesses 328 */ 329#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 330#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 331 332/* 333 * FLASH timing: 334 */ 335#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 336 OR_SCY_3_CLK | OR_EHTR | OR_BI) 337 338#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 339#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 340#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 341 342#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 343#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 344#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 345 346/* 347 * BR2/3 and OR2/3 (SDRAM) 348 * 349 */ 350#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 351#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 352#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 353 354/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 355#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 356 357#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 358#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 359 360#ifndef CONFIG_CAN_DRIVER 361#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 362#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 363#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 364#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 365#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 366#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 367#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 368 BR_PS_8 | BR_MS_UPMB | BR_V ) 369#endif /* CONFIG_CAN_DRIVER */ 370 371/* 372 * Memory Periodic Timer Prescaler 373 * 374 * The Divider for PTA (refresh timer) configuration is based on an 375 * example SDRAM configuration (64 MBit, one bank). The adjustment to 376 * the number of chip selects (NCS) and the actually needed refresh 377 * rate is done by setting MPTPR. 378 * 379 * PTA is calculated from 380 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 381 * 382 * gclk CPU clock (not bus clock!) 383 * Trefresh Refresh cycle * 4 (four word bursts used) 384 * 385 * 4096 Rows from SDRAM example configuration 386 * 1000 factor s -> ms 387 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 388 * 4 Number of refresh cycles per period 389 * 64 Refresh cycle in ms per number of rows 390 * -------------------------------------------- 391 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 392 * 393 * 50 MHz => 50.000.000 / Divider = 98 394 * 66 Mhz => 66.000.000 / Divider = 129 395 * 80 Mhz => 80.000.000 / Divider = 156 396 */ 397 398#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 399#define CONFIG_SYS_MAMR_PTA 98 400 401/* 402 * For 16 MBit, refresh rates could be 31.3 us 403 * (= 64 ms / 2K = 125 / quad bursts). 404 * For a simpler initialization, 15.6 us is used instead. 405 * 406 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 407 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 408 */ 409#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 410#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 411 412/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 413#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 414#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 415 416/* 417 * MAMR settings for SDRAM 418 */ 419 420/* 8 column SDRAM */ 421#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 422 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 423 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 424/* 9 column SDRAM */ 425#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 426 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 427 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 428 429#define CONFIG_HWCONFIG 1 430 431#endif /* __CONFIG_H */ 432