1/* 2 * (C) Copyright 2000-2014 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* 9 * board/config.h - configuration options, board specific 10 */ 11 12#ifndef __CONFIG_H 13#define __CONFIG_H 14 15/* 16 * High Level Configuration Options 17 * (easy to change) 18 */ 19 20#define CONFIG_MPC855 1 /* This is a MPC855 CPU */ 21#define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */ 22 23#define CONFIG_SYS_TEXT_BASE 0x40000000 24 25#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 26#define CONFIG_SYS_SMC_RXBUFLEN 128 27#define CONFIG_SYS_MAXIDLE 10 28 29#define CONFIG_BOOTCOUNT_LIMIT 30 31 32#define CONFIG_BOARD_TYPES 1 /* support board types */ 33 34#define CONFIG_PREBOOT "echo;" \ 35 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 36 "echo" 37 38#undef CONFIG_BOOTARGS 39 40#define CONFIG_EXTRA_ENV_SETTINGS \ 41 "netdev=eth0\0" \ 42 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 43 "nfsroot=${serverip}:${rootpath}\0" \ 44 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 45 "addip=setenv bootargs ${bootargs} " \ 46 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 47 ":${hostname}:${netdev}:off panic=1\0" \ 48 "flash_nfs=run nfsargs addip;" \ 49 "bootm ${kernel_addr}\0" \ 50 "flash_self=run ramargs addip;" \ 51 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 52 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 53 "rootpath=/opt/eldk/ppc_8xx\0" \ 54 "hostname=TQM855M\0" \ 55 "bootfile=TQM855M/uImage\0" \ 56 "fdt_addr=40080000\0" \ 57 "kernel_addr=400A0000\0" \ 58 "ramdisk_addr=40280000\0" \ 59 "u-boot=TQM855M/u-image.bin\0" \ 60 "load=tftp 200000 ${u-boot}\0" \ 61 "update=prot off 40000000 +${filesize};" \ 62 "era 40000000 +${filesize};" \ 63 "cp.b 200000 40000000 ${filesize};" \ 64 "sete filesize;save\0" \ 65 "" 66#define CONFIG_BOOTCOMMAND "run flash_self" 67 68#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 69#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 70 71#undef CONFIG_WATCHDOG /* watchdog disabled */ 72 73#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 74 75/* enable I2C and select the hardware/software driver */ 76#define CONFIG_SYS_I2C 77#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ 78#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */ 79#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE 80/* 81 * Software (bit-bang) I2C driver configuration 82 */ 83#define PB_SCL 0x00000020 /* PB 26 */ 84#define PB_SDA 0x00000010 /* PB 27 */ 85 86#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) 87#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) 88#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) 89#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) 90#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ 91 else immr->im_cpm.cp_pbdat &= ~PB_SDA 92#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ 93 else immr->im_cpm.cp_pbdat &= ~PB_SCL 94#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ 95 96#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */ 97#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ 98#if 0 99#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */ 100#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01 101#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 102#endif 103 104/* 105 * BOOTP options 106 */ 107#define CONFIG_BOOTP_SUBNETMASK 108#define CONFIG_BOOTP_GATEWAY 109#define CONFIG_BOOTP_HOSTNAME 110#define CONFIG_BOOTP_BOOTPATH 111#define CONFIG_BOOTP_BOOTFILESIZE 112 113#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 114 115/* 116 * Command line configuration. 117 */ 118#define CONFIG_CMD_EEPROM 119#define CONFIG_CMD_IDE 120#define CONFIG_CMD_JFFS2 121 122#define CONFIG_NETCONSOLE 123 124/* 125 * Miscellaneous configurable options 126 */ 127#define CONFIG_SYS_LONGHELP /* undef to save memory */ 128 129#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 130 131#if defined(CONFIG_CMD_KGDB) 132#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 133#else 134#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 135#endif 136#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 137#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 138#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 139 140#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 141#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 142 143#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 144 145/* 146 * Low Level Configuration Settings 147 * (address mappings, register initial values, etc.) 148 * You should know what you are doing if you make changes here. 149 */ 150/*----------------------------------------------------------------------- 151 * Internal Memory Mapped Register 152 */ 153#define CONFIG_SYS_IMMR 0xFFF00000 154 155/*----------------------------------------------------------------------- 156 * Definitions for initial stack pointer and data area (in DPRAM) 157 */ 158#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 159#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 160#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 161#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 162 163/*----------------------------------------------------------------------- 164 * Start addresses for the final memory configuration 165 * (Set up by the startup code) 166 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 167 */ 168#define CONFIG_SYS_SDRAM_BASE 0x00000000 169#define CONFIG_SYS_FLASH_BASE 0x40000000 170#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 171#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 172#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 173 174/* 175 * For booting Linux, the board info and command line data 176 * have to be in the first 8 MB of memory, since this is 177 * the maximum mapped by the Linux kernel during initialization. 178 */ 179#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 180 181/*----------------------------------------------------------------------- 182 * FLASH organization 183 */ 184 185/* use CFI flash driver */ 186#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 187#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 188#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 189#define CONFIG_SYS_FLASH_EMPTY_INFO 190#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 191#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 192#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 193 194#define CONFIG_ENV_IS_IN_FLASH 1 195#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ 196#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ 197#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ 198 199/* Address and size of Redundant Environment Sector */ 200#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) 201#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 202 203#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 204 205#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 206 207/*----------------------------------------------------------------------- 208 * Dynamic MTD partition support 209 */ 210#define CONFIG_CMD_MTDPARTS 211#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 212#define CONFIG_FLASH_CFI_MTD 213#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" 214 215#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ 216 "128k(dtb)," \ 217 "1920k(kernel)," \ 218 "5632(rootfs)," \ 219 "4m(data)" 220 221/*----------------------------------------------------------------------- 222 * Hardware Information Block 223 */ 224#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 225#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 226#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 227 228/*----------------------------------------------------------------------- 229 * Cache Configuration 230 */ 231#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 232#if defined(CONFIG_CMD_KGDB) 233#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 234#endif 235 236/*----------------------------------------------------------------------- 237 * SYPCR - System Protection Control 11-9 238 * SYPCR can only be written once after reset! 239 *----------------------------------------------------------------------- 240 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 241 */ 242#if defined(CONFIG_WATCHDOG) 243#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 244 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 245#else 246#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 247#endif 248 249/*----------------------------------------------------------------------- 250 * SIUMCR - SIU Module Configuration 11-6 251 *----------------------------------------------------------------------- 252 * PCMCIA config., multi-function pin tri-state 253 */ 254#ifndef CONFIG_CAN_DRIVER 255#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 256#else /* we must activate GPL5 in the SIUMCR for CAN */ 257#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 258#endif /* CONFIG_CAN_DRIVER */ 259 260/*----------------------------------------------------------------------- 261 * TBSCR - Time Base Status and Control 11-26 262 *----------------------------------------------------------------------- 263 * Clear Reference Interrupt Status, Timebase freezing enabled 264 */ 265#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 266 267/*----------------------------------------------------------------------- 268 * RTCSC - Real-Time Clock Status and Control Register 11-27 269 *----------------------------------------------------------------------- 270 */ 271#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 272 273/*----------------------------------------------------------------------- 274 * PISCR - Periodic Interrupt Status and Control 11-31 275 *----------------------------------------------------------------------- 276 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 277 */ 278#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 279 280/*----------------------------------------------------------------------- 281 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 282 *----------------------------------------------------------------------- 283 * Reset PLL lock status sticky bit, timer expired status bit and timer 284 * interrupt status bit 285 */ 286#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 287 288/*----------------------------------------------------------------------- 289 * SCCR - System Clock and reset Control Register 15-27 290 *----------------------------------------------------------------------- 291 * Set clock output, timebase and RTC source and divider, 292 * power management and some other internal clocks 293 */ 294#define SCCR_MASK SCCR_EBDF11 295#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 296 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 297 SCCR_DFALCD00) 298 299/*----------------------------------------------------------------------- 300 * PCMCIA stuff 301 *----------------------------------------------------------------------- 302 * 303 */ 304#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 305#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 306#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 307#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 308#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 309#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 310#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 311#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 312 313/*----------------------------------------------------------------------- 314 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 315 *----------------------------------------------------------------------- 316 */ 317 318#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ 319#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 320 321#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 322#undef CONFIG_IDE_LED /* LED for ide not supported */ 323#undef CONFIG_IDE_RESET /* reset for ide not supported */ 324 325#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 326#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 327 328#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 329 330#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 331 332/* Offset for data I/O */ 333#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 334 335/* Offset for normal register accesses */ 336#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 337 338/* Offset for alternate registers */ 339#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 340 341/*----------------------------------------------------------------------- 342 * 343 *----------------------------------------------------------------------- 344 * 345 */ 346#define CONFIG_SYS_DER 0 347 348/* 349 * Init Memory Controller: 350 * 351 * BR0/1 and OR0/1 (FLASH) 352 */ 353 354#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 355#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 356 357/* used to re-map FLASH both when starting from SRAM or FLASH: 358 * restrict access enough to keep SRAM working (if any) 359 * but not too much to meddle with FLASH accesses 360 */ 361#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 362#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 363 364/* 365 * FLASH timing: 366 */ 367#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 368 OR_SCY_3_CLK | OR_EHTR | OR_BI) 369 370#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 371#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 372#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 373 374#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 375#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 376#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 377 378/* 379 * BR2/3 and OR2/3 (SDRAM) 380 * 381 */ 382#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 383#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 384#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 385 386/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 387#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 388 389#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 390#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 391 392#ifndef CONFIG_CAN_DRIVER 393#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 394#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 395#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 396#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 397#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 398#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 399#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 400 BR_PS_8 | BR_MS_UPMB | BR_V ) 401#endif /* CONFIG_CAN_DRIVER */ 402 403/* 404 * Memory Periodic Timer Prescaler 405 * 406 * The Divider for PTA (refresh timer) configuration is based on an 407 * example SDRAM configuration (64 MBit, one bank). The adjustment to 408 * the number of chip selects (NCS) and the actually needed refresh 409 * rate is done by setting MPTPR. 410 * 411 * PTA is calculated from 412 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 413 * 414 * gclk CPU clock (not bus clock!) 415 * Trefresh Refresh cycle * 4 (four word bursts used) 416 * 417 * 4096 Rows from SDRAM example configuration 418 * 1000 factor s -> ms 419 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 420 * 4 Number of refresh cycles per period 421 * 64 Refresh cycle in ms per number of rows 422 * -------------------------------------------- 423 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 424 * 425 * 50 MHz => 50.000.000 / Divider = 98 426 * 66 Mhz => 66.000.000 / Divider = 129 427 * 80 Mhz => 80.000.000 / Divider = 156 428 */ 429 430#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 431#define CONFIG_SYS_MAMR_PTA 98 432 433/* 434 * For 16 MBit, refresh rates could be 31.3 us 435 * (= 64 ms / 2K = 125 / quad bursts). 436 * For a simpler initialization, 15.6 us is used instead. 437 * 438 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 439 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 440 */ 441#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 442#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 443 444/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 445#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 446#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 447 448/* 449 * MAMR settings for SDRAM 450 */ 451 452/* 8 column SDRAM */ 453#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 454 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 455 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 456/* 9 column SDRAM */ 457#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 458 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 459 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 460 461#define CONFIG_SCC1_ENET 462#define CONFIG_FEC_ENET 463#define CONFIG_ETHPRIME "SCC" 464 465#define CONFIG_HWCONFIG 1 466 467#endif /* __CONFIG_H */ 468