1/* 2 * (C) Copyright 2000-2014 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* 9 * board/config.h - configuration options, board specific 10 */ 11 12#ifndef __CONFIG_H 13#define __CONFIG_H 14 15/* 16 * High Level Configuration Options 17 * (easy to change) 18 */ 19 20#define CONFIG_MPC860 1 21#define CONFIG_MPC860T 1 22#define CONFIG_MPC862 1 23 24#define CONFIG_TQM862L 1 /* ...on a TQM8xxL module */ 25 26#define CONFIG_SYS_TEXT_BASE 0x40000000 27 28#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 29#define CONFIG_SYS_SMC_RXBUFLEN 128 30#define CONFIG_SYS_MAXIDLE 10 31 32#define CONFIG_BOOTCOUNT_LIMIT 33 34 35#define CONFIG_BOARD_TYPES 1 /* support board types */ 36 37#define CONFIG_PREBOOT "echo;" \ 38 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 39 "echo" 40 41#undef CONFIG_BOOTARGS 42 43#define CONFIG_EXTRA_ENV_SETTINGS \ 44 "netdev=eth0\0" \ 45 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 46 "nfsroot=${serverip}:${rootpath}\0" \ 47 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 48 "addip=setenv bootargs ${bootargs} " \ 49 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 50 ":${hostname}:${netdev}:off panic=1\0" \ 51 "flash_nfs=run nfsargs addip;" \ 52 "bootm ${kernel_addr}\0" \ 53 "flash_self=run ramargs addip;" \ 54 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 55 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 56 "rootpath=/opt/eldk/ppc_8xx\0" \ 57 "hostname=TQM862L\0" \ 58 "bootfile=TQM862L/uImage\0" \ 59 "fdt_addr=40040000\0" \ 60 "kernel_addr=40060000\0" \ 61 "ramdisk_addr=40200000\0" \ 62 "u-boot=TQM862L/u-image.bin\0" \ 63 "load=tftp 200000 ${u-boot}\0" \ 64 "update=prot off 40000000 +${filesize};" \ 65 "era 40000000 +${filesize};" \ 66 "cp.b 200000 40000000 ${filesize};" \ 67 "sete filesize;save\0" \ 68 "" 69#define CONFIG_BOOTCOMMAND "run flash_self" 70 71#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 72#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 73 74#undef CONFIG_WATCHDOG /* watchdog disabled */ 75 76#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 77 78/* 79 * BOOTP options 80 */ 81#define CONFIG_BOOTP_SUBNETMASK 82#define CONFIG_BOOTP_GATEWAY 83#define CONFIG_BOOTP_HOSTNAME 84#define CONFIG_BOOTP_BOOTPATH 85#define CONFIG_BOOTP_BOOTFILESIZE 86 87#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 88 89/* 90 * Command line configuration. 91 */ 92#define CONFIG_CMD_IDE 93#define CONFIG_CMD_JFFS2 94 95#define CONFIG_NETCONSOLE 96 97/* 98 * Miscellaneous configurable options 99 */ 100#define CONFIG_SYS_LONGHELP /* undef to save memory */ 101 102#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 103 104#if defined(CONFIG_CMD_KGDB) 105#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 106#else 107#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 108#endif 109#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 110#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 111#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 112 113#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 114#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 115 116#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 117 118/* 119 * Low Level Configuration Settings 120 * (address mappings, register initial values, etc.) 121 * You should know what you are doing if you make changes here. 122 */ 123/*----------------------------------------------------------------------- 124 * Internal Memory Mapped Register 125 */ 126#define CONFIG_SYS_IMMR 0xFFF00000 127 128/*----------------------------------------------------------------------- 129 * Definitions for initial stack pointer and data area (in DPRAM) 130 */ 131#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 132#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 133#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 134#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 135 136/*----------------------------------------------------------------------- 137 * Start addresses for the final memory configuration 138 * (Set up by the startup code) 139 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 140 */ 141#define CONFIG_SYS_SDRAM_BASE 0x00000000 142#define CONFIG_SYS_FLASH_BASE 0x40000000 143#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 144#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 145#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 146 147/* 148 * For booting Linux, the board info and command line data 149 * have to be in the first 8 MB of memory, since this is 150 * the maximum mapped by the Linux kernel during initialization. 151 */ 152#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 153 154/*----------------------------------------------------------------------- 155 * FLASH organization 156 */ 157 158/* use CFI flash driver */ 159#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 160#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 161#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } 162#define CONFIG_SYS_FLASH_EMPTY_INFO 163#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 164#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 165#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ 166 167#define CONFIG_ENV_IS_IN_FLASH 1 168#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ 169#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ 170 171/* Address and size of Redundant Environment Sector */ 172#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) 173#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 174 175#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 176 177#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 178 179/*----------------------------------------------------------------------- 180 * Dynamic MTD partition support 181 */ 182#define CONFIG_CMD_MTDPARTS 183#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 184#define CONFIG_FLASH_CFI_MTD 185#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" 186 187#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ 188 "128k(dtb)," \ 189 "1664k(kernel)," \ 190 "2m(rootfs)," \ 191 "4m(data)" 192 193/*----------------------------------------------------------------------- 194 * Hardware Information Block 195 */ 196#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 197#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 198#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 199 200/*----------------------------------------------------------------------- 201 * Cache Configuration 202 */ 203#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 204#if defined(CONFIG_CMD_KGDB) 205#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 206#endif 207 208/*----------------------------------------------------------------------- 209 * SYPCR - System Protection Control 11-9 210 * SYPCR can only be written once after reset! 211 *----------------------------------------------------------------------- 212 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 213 */ 214#if defined(CONFIG_WATCHDOG) 215#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 216 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 217#else 218#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 219#endif 220 221/*----------------------------------------------------------------------- 222 * SIUMCR - SIU Module Configuration 11-6 223 *----------------------------------------------------------------------- 224 * PCMCIA config., multi-function pin tri-state 225 */ 226#ifndef CONFIG_CAN_DRIVER 227#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 228#else /* we must activate GPL5 in the SIUMCR for CAN */ 229#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 230#endif /* CONFIG_CAN_DRIVER */ 231 232/*----------------------------------------------------------------------- 233 * TBSCR - Time Base Status and Control 11-26 234 *----------------------------------------------------------------------- 235 * Clear Reference Interrupt Status, Timebase freezing enabled 236 */ 237#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 238 239/*----------------------------------------------------------------------- 240 * RTCSC - Real-Time Clock Status and Control Register 11-27 241 *----------------------------------------------------------------------- 242 */ 243#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 244 245/*----------------------------------------------------------------------- 246 * PISCR - Periodic Interrupt Status and Control 11-31 247 *----------------------------------------------------------------------- 248 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 249 */ 250#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 251 252/*----------------------------------------------------------------------- 253 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 254 *----------------------------------------------------------------------- 255 * Reset PLL lock status sticky bit, timer expired status bit and timer 256 * interrupt status bit 257 */ 258#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 259 260/*----------------------------------------------------------------------- 261 * SCCR - System Clock and reset Control Register 15-27 262 *----------------------------------------------------------------------- 263 * Set clock output, timebase and RTC source and divider, 264 * power management and some other internal clocks 265 */ 266#define SCCR_MASK SCCR_EBDF11 267#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 268 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 269 SCCR_DFALCD00) 270 271/*----------------------------------------------------------------------- 272 * PCMCIA stuff 273 *----------------------------------------------------------------------- 274 * 275 */ 276#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 277#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 278#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 279#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 280#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 281#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 282#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 283#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 284 285/*----------------------------------------------------------------------- 286 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 287 *----------------------------------------------------------------------- 288 */ 289 290#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ 291#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 292 293#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 294#undef CONFIG_IDE_LED /* LED for ide not supported */ 295#undef CONFIG_IDE_RESET /* reset for ide not supported */ 296 297#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 298#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 299 300#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 301 302#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 303 304/* Offset for data I/O */ 305#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 306 307/* Offset for normal register accesses */ 308#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 309 310/* Offset for alternate registers */ 311#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 312 313/*----------------------------------------------------------------------- 314 * 315 *----------------------------------------------------------------------- 316 * 317 */ 318#define CONFIG_SYS_DER 0 319 320/* 321 * Init Memory Controller: 322 * 323 * BR0/1 and OR0/1 (FLASH) 324 */ 325 326#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 327#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */ 328 329/* used to re-map FLASH both when starting from SRAM or FLASH: 330 * restrict access enough to keep SRAM working (if any) 331 * but not too much to meddle with FLASH accesses 332 */ 333#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 334#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 335 336/* 337 * FLASH timing: 338 */ 339#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 340 OR_SCY_3_CLK | OR_EHTR | OR_BI) 341 342#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 343#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 344#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 345 346#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 347#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 348#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 349 350/* 351 * BR2/3 and OR2/3 (SDRAM) 352 * 353 */ 354#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 355#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 356#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 357 358/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 359#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 360 361#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 362#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 363 364#ifndef CONFIG_CAN_DRIVER 365#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 366#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 367#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 368#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 369#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 370#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 371#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 372 BR_PS_8 | BR_MS_UPMB | BR_V ) 373#endif /* CONFIG_CAN_DRIVER */ 374 375/* 376 * Memory Periodic Timer Prescaler 377 * 378 * The Divider for PTA (refresh timer) configuration is based on an 379 * example SDRAM configuration (64 MBit, one bank). The adjustment to 380 * the number of chip selects (NCS) and the actually needed refresh 381 * rate is done by setting MPTPR. 382 * 383 * PTA is calculated from 384 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 385 * 386 * gclk CPU clock (not bus clock!) 387 * Trefresh Refresh cycle * 4 (four word bursts used) 388 * 389 * 4096 Rows from SDRAM example configuration 390 * 1000 factor s -> ms 391 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 392 * 4 Number of refresh cycles per period 393 * 64 Refresh cycle in ms per number of rows 394 * -------------------------------------------- 395 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 396 * 397 * 50 MHz => 50.000.000 / Divider = 98 398 * 66 Mhz => 66.000.000 / Divider = 129 399 * 80 Mhz => 80.000.000 / Divider = 156 400 * 100 Mhz => 100.000.000 / Divider = 195 401 */ 402 403#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 404#define CONFIG_SYS_MAMR_PTA 98 405 406/* 407 * For 16 MBit, refresh rates could be 31.3 us 408 * (= 64 ms / 2K = 125 / quad bursts). 409 * For a simpler initialization, 15.6 us is used instead. 410 * 411 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 412 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 413 */ 414#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 415#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 416 417/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 418#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 419#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 420 421/* 422 * MAMR settings for SDRAM 423 */ 424 425/* 8 column SDRAM */ 426#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 427 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 428 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 429/* 9 column SDRAM */ 430#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 431 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 432 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 433 434#define CONFIG_SCC1_ENET 435#define CONFIG_FEC_ENET 436#define CONFIG_ETHPRIME "SCC" 437 438#define CONFIG_HWCONFIG 1 439 440#endif /* __CONFIG_H */ 441