1/* 2 * (C) Copyright 2000-2014 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * (C) Copyright 2006 6 * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11/* 12 * board/config.h - configuration options, board specific 13 */ 14 15#ifndef __CONFIG_H 16#define __CONFIG_H 17 18/* 19 * High Level Configuration Options 20 * (easy to change) 21 */ 22 23#define CONFIG_MPC885 1 /* This is a MPC885 CPU */ 24#define CONFIG_TQM885D 1 /* ...on a TQM88D module */ 25 26#define CONFIG_SYS_TEXT_BASE 0x40000000 27 28#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ 29#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ 30#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ 31#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 66 MHz - CPU default clock */ 32 /* (it will be used if there is no */ 33 /* 'cpuclk' variable with valid value) */ 34 35#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 36#define CONFIG_SYS_SMC_RXBUFLEN 128 37#define CONFIG_SYS_MAXIDLE 10 38 39#define CONFIG_BOOTCOUNT_LIMIT 40 41 42#define CONFIG_BOARD_TYPES 1 /* support board types */ 43 44#define CONFIG_PREBOOT "echo;" \ 45 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 46 "echo" 47 48#undef CONFIG_BOOTARGS 49 50#define CONFIG_EXTRA_ENV_SETTINGS \ 51 "netdev=eth0\0" \ 52 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 53 "nfsroot=${serverip}:${rootpath}\0" \ 54 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 55 "addip=setenv bootargs ${bootargs} " \ 56 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 57 ":${hostname}:${netdev}:off panic=1\0" \ 58 "flash_nfs=run nfsargs addip;" \ 59 "bootm ${kernel_addr}\0" \ 60 "flash_self=run ramargs addip;" \ 61 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 62 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 63 "rootpath=/opt/eldk/ppc_8xx\0" \ 64 "bootfile=/tftpboot/TQM885D/uImage\0" \ 65 "fdt_addr=400C0000\0" \ 66 "kernel_addr=40100000\0" \ 67 "ramdisk_addr=40280000\0" \ 68 "load=tftp 200000 ${u-boot}\0" \ 69 "update=protect off 40000000 +${filesize};" \ 70 "erase 40000000 +${filesize};" \ 71 "cp.b 200000 40000000 ${filesize};" \ 72 "protect on 40000000 +${filesize}\0" \ 73 "" 74#define CONFIG_BOOTCOMMAND "run flash_self" 75 76#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 77#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 78 79#undef CONFIG_WATCHDOG /* watchdog disabled */ 80 81#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 82 83/* enable I2C and select the hardware/software driver */ 84#define CONFIG_SYS_I2C 85#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ 86#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */ 87#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE 88/* 89 * Software (bit-bang) I2C driver configuration 90 */ 91#define PB_SCL 0x00000020 /* PB 26 */ 92#define PB_SDA 0x00000010 /* PB 27 */ 93 94#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) 95#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) 96#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) 97#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) 98#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ 99 else immr->im_cpm.cp_pbdat &= ~PB_SDA 100#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ 101 else immr->im_cpm.cp_pbdat &= ~PB_SCL 102#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ 103 104#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */ 105#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ 106#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 107#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ 108 109# define CONFIG_RTC_DS1337 1 110# define CONFIG_SYS_I2C_RTC_ADDR 0x68 111 112/* 113 * BOOTP options 114 */ 115#define CONFIG_BOOTP_SUBNETMASK 116#define CONFIG_BOOTP_GATEWAY 117#define CONFIG_BOOTP_HOSTNAME 118#define CONFIG_BOOTP_BOOTPATH 119#define CONFIG_BOOTP_BOOTFILESIZE 120 121#undef CONFIG_RTC_MPC8xx /* MPC885 does not support RTC */ 122 123#define CONFIG_TIMESTAMP /* but print image timestmps */ 124 125/* 126 * Command line configuration. 127 */ 128#define CONFIG_CMD_EEPROM 129#define CONFIG_CMD_IDE 130 131/* 132 * Miscellaneous configurable options 133 */ 134#define CONFIG_SYS_LONGHELP /* undef to save memory */ 135 136#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 137 138#if defined(CONFIG_CMD_KGDB) 139#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 140#else 141#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 142#endif 143#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 144#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 145#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 146 147#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ 148#define CONFIG_SYS_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */ 149#define CONFIG_SYS_ALT_MEMTEST /* alternate, more extensive 150 memory test.*/ 151 152#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 153 154/* 155 * Low Level Configuration Settings 156 * (address mappings, register initial values, etc.) 157 * You should know what you are doing if you make changes here. 158 */ 159/*----------------------------------------------------------------------- 160 * Internal Memory Mapped Register 161 */ 162#define CONFIG_SYS_IMMR 0xFFF00000 163 164/*----------------------------------------------------------------------- 165 * Definitions for initial stack pointer and data area (in DPRAM) 166 */ 167#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 168#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 169#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 170#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 171 172/*----------------------------------------------------------------------- 173 * Start addresses for the final memory configuration 174 * (Set up by the startup code) 175 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 176 */ 177#define CONFIG_SYS_SDRAM_BASE 0x00000000 178#define CONFIG_SYS_FLASH_BASE 0x40000000 179#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 180#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 181#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */ 182 183/* 184 * For booting Linux, the board info and command line data 185 * have to be in the first 8 MB of memory, since this is 186 * the maximum mapped by the Linux kernel during initialization. 187 */ 188#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 189 190/*----------------------------------------------------------------------- 191 * FLASH organization 192 */ 193 194/* use CFI flash driver */ 195#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 196#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 197#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 198#define CONFIG_SYS_FLASH_EMPTY_INFO 199#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 200#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 201#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 202 203#define CONFIG_ENV_IS_IN_FLASH 1 204#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ 205#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ 206#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ 207 208/* Address and size of Redundant Environment Sector */ 209#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) 210#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 211 212/*----------------------------------------------------------------------- 213 * Hardware Information Block 214 */ 215#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 216#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 217#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 218 219/*----------------------------------------------------------------------- 220 * Cache Configuration 221 */ 222#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 223#if defined(CONFIG_CMD_KGDB) 224#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 225#endif 226 227/*----------------------------------------------------------------------- 228 * SYPCR - System Protection Control 11-9 229 * SYPCR can only be written once after reset! 230 *----------------------------------------------------------------------- 231 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 232 */ 233#if defined(CONFIG_WATCHDOG) 234#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 235 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 236#else 237#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 238#endif 239 240/*----------------------------------------------------------------------- 241 * SIUMCR - SIU Module Configuration 11-6 242 *----------------------------------------------------------------------- 243 * PCMCIA config., multi-function pin tri-state 244 */ 245#ifndef CONFIG_CAN_DRIVER 246#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 247#else /* we must activate GPL5 in the SIUMCR for CAN */ 248#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 249#endif /* CONFIG_CAN_DRIVER */ 250 251/*----------------------------------------------------------------------- 252 * TBSCR - Time Base Status and Control 11-26 253 *----------------------------------------------------------------------- 254 * Clear Reference Interrupt Status, Timebase freezing enabled 255 */ 256#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 257 258/*----------------------------------------------------------------------- 259 * PISCR - Periodic Interrupt Status and Control 11-31 260 *----------------------------------------------------------------------- 261 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 262 */ 263#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 264 265/*----------------------------------------------------------------------- 266 * SCCR - System Clock and reset Control Register 15-27 267 *----------------------------------------------------------------------- 268 * Set clock output, timebase and RTC source and divider, 269 * power management and some other internal clocks 270 */ 271#define SCCR_MASK SCCR_EBDF11 272#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 273 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 274 SCCR_DFALCD00) 275 276/*----------------------------------------------------------------------- 277 * PCMCIA stuff 278 *----------------------------------------------------------------------- 279 * 280 */ 281#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 282#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 283#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 284#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 285#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 286#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 287#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 288#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 289 290/*----------------------------------------------------------------------- 291 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 292 *----------------------------------------------------------------------- 293 */ 294 295#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ 296#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 297 298#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 299#undef CONFIG_IDE_LED /* LED for ide not supported */ 300#undef CONFIG_IDE_RESET /* reset for ide not supported */ 301 302#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 303#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 304 305#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 306 307#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 308 309/* Offset for data I/O */ 310#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 311 312/* Offset for normal register accesses */ 313#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 314 315/* Offset for alternate registers */ 316#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 317 318/*----------------------------------------------------------------------- 319 * 320 *----------------------------------------------------------------------- 321 * 322 */ 323#define CONFIG_SYS_DER 0 324 325/* 326 * Init Memory Controller: 327 * 328 * BR0/1 and OR0/1 (FLASH) 329 */ 330 331#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 332#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 333 334/* used to re-map FLASH both when starting from SRAM or FLASH: 335 * restrict access enough to keep SRAM working (if any) 336 * but not too much to meddle with FLASH accesses 337 */ 338#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 339#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 340 341/* 342 * FLASH timing: Default value of OR0 after reset 343 */ 344#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ 345 OR_SCY_6_CLK | OR_TRLX) 346 347#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 348#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 349#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 350 351#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 352#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 353#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 354 355/* 356 * BR2/3 and OR2/3 (SDRAM) 357 * 358 */ 359#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 360#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 361#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */ 362 363/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 364#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 365 366#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 367#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 368 369#ifndef CONFIG_CAN_DRIVER 370#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 371#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 372#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 373#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 374#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 375#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 376#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 377 BR_PS_8 | BR_MS_UPMB | BR_V ) 378#endif /* CONFIG_CAN_DRIVER */ 379 380/* 381 * 4096 Rows from SDRAM example configuration 382 * 1000 factor s -> ms 383 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration 384 * 4 Number of refresh cycles per period 385 * 64 Refresh cycle in ms per number of rows 386 */ 387#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) 388 389/* 390 * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad) 391 * 392 * CPUclock(MHz) * 31.2 393 * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0 394 * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16 395 * 396 * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us 397 * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us 398 * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us 399 * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us 400 * 401 * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will 402 * be met also in the default configuration, i.e. if environment variable 403 * 'cpuclk' is not set. 404 */ 405#define CONFIG_SYS_MAMR_PTA 128 406 407/* 408 * Memory Periodic Timer Prescaler Register (MPTPR) values. 409 */ 410/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */ 411#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 412/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */ 413#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 414 415/* 416 * MAMR settings for SDRAM 417 */ 418 419/* 8 column SDRAM */ 420#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 421 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 422 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 423/* 9 column SDRAM */ 424#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 425 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 426 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 427/* 10 column SDRAM */ 428#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 429 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ 430 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 431 432/* 433 * Network configuration 434 */ 435#define CONFIG_SCC2_ENET /* enable ethernet on SCC2 */ 436#define CONFIG_FEC_ENET /* enable ethernet on FEC */ 437#define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */ 438#define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */ 439 440#if defined(CONFIG_CMD_MII) 441#define CONFIG_SYS_DISCOVER_PHY 442#define CONFIG_MII_INIT 1 443#endif 444 445#define CONFIG_NET_RETRY_COUNT 1 /* reduce max. timeout before 446 switching to another netwok (if the 447 tried network is unreachable) */ 448 449#define CONFIG_ETHPRIME "SCC" 450 451#define CONFIG_HWCONFIG 1 452 453#endif /* __CONFIG_H */ 454